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authorReka Norman <rekanorman@chromium.org>2022-07-07 15:30:22 +1000
committerFelix Held <felix-coreboot@felixheld.de>2022-07-08 15:28:59 +0000
commit8bbc5ba0aef5ba57ca5bac1873619047d8466bf9 (patch)
tree1fceeb4a470f646bc1c31161b7f49629d3cd03f0
parentb146c7a7c0b1ad78d7171bf88111be93ce233b03 (diff)
soc/intel/common/pch: Fix incorrect GPE number
BUG=None TEST=None Change-Id: I7a4081f0f57e0faa968ad142debdc40a9e26dc9b Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65690 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/common/pch/include/intelpch/gpe.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/pch/include/intelpch/gpe.h b/src/soc/intel/common/pch/include/intelpch/gpe.h
index 2e3f44ab17..01f4128b69 100644
--- a/src/soc/intel/common/pch/include/intelpch/gpe.h
+++ b/src/soc/intel/common/pch/include/intelpch/gpe.h
@@ -40,7 +40,7 @@
#define GPE0_DW1_00 32
#define GPE0_DW1_01 33
#define GPE0_DW1_02 34
-#define GPE0_DW1_03 36
+#define GPE0_DW1_03 35
#define GPE0_DW1_04 36
#define GPE0_DW1_05 37
#define GPE0_DW1_06 38