diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-25 01:04:51 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-10-14 08:38:42 +0000 |
| commit | 8b8b271f12941742c723c136d8a3a901302e7856 (patch) | |
| tree | 4ff45812e89100b97b07a63e9c0c19950ce90fb1 | |
| parent | 3b8b00fd39b3dbbf42b41a018e2bdf264479fc97 (diff) | |
soc/intel/broadwell/xhci.c: Align with Lynx Point
Change-Id: Idf40e2687b064c5ec7834e3c7d7ea9c8cb83c882
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45721
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/broadwell/xhci.c | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 319c9b125b..526781d1c4 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -129,7 +129,6 @@ static void usb_xhci_reset_usb3(pci_devfn_t dev, int all) /* Handler for XHCI controller on entry to S3/S4/S5 */ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) { - u16 reg16; u32 reg32; u8 *mem_base = usb_xhci_mem_base(dev); u8 is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); @@ -138,18 +137,13 @@ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) return; /* Set D0 state */ - reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); - reg16 &= ~XHCI_PWR_CTL_SET_MASK; - reg16 |= XHCI_PWR_CTL_SET_D0; - pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); + pci_update_config16(dev, XHCI_PWR_CTL_STS, ~XHCI_PWR_CTL_SET_MASK, XHCI_PWR_CTL_SET_D0); if (!is_broadwell) { /* This WA is only for lpt */ /* Clear PCI 0xB0[14:13] */ - reg32 = pci_read_config32(dev, 0xb0); - reg32 &= ~((1 << 14) | (1 << 13)); - pci_write_config32(dev, 0xb0, reg32); + pci_and_config32(dev, 0xb0, ~((1 << 14) | (1 << 13))); /* Clear MMIO 0x816c[14,2] */ reg32 = read32(mem_base + 0x816c); |