soc/intel/{icl,tgl,jsl,ehl}: add LPIT support

Add SLP_S0 residency register and enable LPIT support.

Change-Id: Id1abbe8dcb7796eeb26ccb72f1f26cf7a040dba4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49048
Reviewed-by: Lance Zhao
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 12 insertions, 0 deletions

diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index 3031769873..25aea15b07 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -40,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK
 	select SOC_INTEL_COMMON_BLOCK_ACPI
+	select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
 	select SOC_INTEL_COMMON_BLOCK_CAR
 	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
 	select SOC_INTEL_COMMON_BLOCK_CPU
diff --git a/src/soc/intel/elkhartlake/include/soc/pmc.h b/src/soc/intel/elkhartlake/include/soc/pmc.h
index f331961898..1c8cb1a674 100644
--- a/src/soc/intel/elkhartlake/include/soc/pmc.h
+++ b/src/soc/intel/elkhartlake/include/soc/pmc.h
@@ -123,6 +123,8 @@
 #define   GBLRST_CAUSE0_THERMTRIP	(1 << 5)
 #define GBLRST_CAUSE1			0x1928
 
+#define SLP_S0_RES			0x193c
+
 #define CPPMVRIC			0x1B1C
 #define   XTALSDQDIS			(1 << 22)
 
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 06c1a9b83e..d1efa5570e 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK
 	select SOC_INTEL_COMMON_BLOCK_ACPI
+	select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
 	select SOC_INTEL_COMMON_BLOCK_CAR
 	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
 	select SOC_INTEL_COMMON_BLOCK_CNVI
diff --git a/src/soc/intel/icelake/include/soc/pmc.h b/src/soc/intel/icelake/include/soc/pmc.h
index 26dae7e58d..2ca3328392 100644
--- a/src/soc/intel/icelake/include/soc/pmc.h
+++ b/src/soc/intel/icelake/include/soc/pmc.h
@@ -119,6 +119,8 @@
 #define   GBLRST_CAUSE0_THERMTRIP	(1 << 5)
 #define GBLRST_CAUSE1			0x1928
 
+#define SLP_S0_RES			0x193c
+
 #define CPPMVRIC			0x1B1C
 #define   XTALSDQDIS			(1 << 22)
 
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 0a15f052d9..9e15a503f2 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -40,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK
 	select SOC_INTEL_COMMON_BLOCK_ACPI
+	select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
 	select SOC_INTEL_COMMON_BLOCK_CAR
 	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
 	select SOC_INTEL_COMMON_BLOCK_CNVI
diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h
index e65e884e64..1df2c63ab8 100644
--- a/src/soc/intel/jasperlake/include/soc/pmc.h
+++ b/src/soc/intel/jasperlake/include/soc/pmc.h
@@ -119,6 +119,8 @@
 #define   GBLRST_CAUSE0_THERMTRIP	(1 << 5)
 #define GBLRST_CAUSE1			0x1928
 
+#define SLP_S0_RES			0x193c
+
 #define CPPMVRIC			0x1B1C
 #define   XTALSDQDIS			(1 << 22)
 
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index c7e10a9a69..9d073fa5f9 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -43,6 +43,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK
 	select SOC_INTEL_COMMON_BLOCK_ACPI
+	select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
 	select SOC_INTEL_COMMON_BLOCK_CAR
 	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
 	select SOC_INTEL_COMMON_BLOCK_CNVI
diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h
index f926799c75..cd0299aa48 100644
--- a/src/soc/intel/tigerlake/include/soc/pmc.h
+++ b/src/soc/intel/tigerlake/include/soc/pmc.h
@@ -152,6 +152,8 @@ enum pch_pmc_xtal pmc_get_xtal_freq(void);
 #define   HPR_CAUSE0_MI_HRPC		(1 << 9)
 #define   HPR_CAUSE0_MI_HR		(1 << 8)
 
+#define SLP_S0_RES			0x193c
+
 #define CPPMVRIC			0x1B1C
 #define   XTALSDQDIS			(1 << 22)