diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-07-27 17:58:02 +0000 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-07-29 15:03:01 +0000 |
| commit | 8a039031dd69e7c6d970eef1e8841aae5c888b0d (patch) | |
| tree | 04e9fb6b41b1df8f6b9d21435dd5805ce6a0d1fb | |
| parent | ff424fbe6be2e01fa6a8f50764d97458e1eba691 (diff) | |
mb/google/rex: Enable CNVi BT Core
This patch override `CnviBtCore` FSP UPD.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I90c9b360969aada0b0e031d62b48476fac5cee0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
| -rw-r--r-- | src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index e669c128dd..3471c7e805 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -11,6 +11,9 @@ chip soc/intel/meteorlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + # Enable CNVi BT + register "cnvi_bt_core" = "true" + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, [PchSerialIoIndexUART1] = PchSerialIoDisabled, |