diff options
author | Caveh Jalali <caveh@chromium.org> | 2020-09-12 03:05:48 -0700 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-21 08:07:13 +0000 |
commit | 85e4c43b02da1561a6af589bdc21fdaa0f112777 (patch) | |
tree | 754f0273dafb10ba84c5df4bc98fa40fbc8fab4e | |
parent | 362bcee0f4496fc60d29eb560a0d26f28e62c31d (diff) |
volteer: set GSPI CS to deasserted by default
This sets the state of GSPI chip select to 1 (deasserted) as applied
by the FSP during the silicon init phase. GSPI 0 and 1 are set to CS
mode manual in the SerialIoGSpiCsMode section which means we need to
explicitly configure CS to deasserted in the SerialIoGSpiCsState
section. GSPI0 is the CR50 and GSPI1 is the fingerprint sensor. We
were running into problems where the normal expected CS toggle
sequence to wake up CR50 did not work because CS was already asserted
when it was expected to be deasserted, leading to TPM timeouts.
BUG=b:168090038
TEST=booted on volteer, no more "TPM flow control failure" messages;
verified fingerprint enrollment still works.
Change-Id: I47aa5db429d75e66095d58a1eb77963dcfc3b9f3
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45384
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 3c1c5f0f63..11542f8964 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -142,8 +142,8 @@ chip soc/intel/tigerlake }" register "SerialIoGSpiCsState" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" |