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authorMatt DeVillier <matt.devillier@gmail.com>2020-04-23 00:46:56 -0500
committerMatt DeVillier <matt.devillier@gmail.com>2020-04-28 08:02:57 +0000
commit8536072346efa0919f82c7355a1cf03147dda8b9 (patch)
tree6e28b38e83c24f4af74edc3677f5ec1e7f2b4d85
parentec926e080303b8b018ed127a1c8af8c78f6c4da9 (diff)
soc/baytrail/raminit: Populate SMBIOS type 17 tables
Populate SMBIOS type 17 tables using data from SPD and read via IOSF. Refactor print_dram_info() to pass thru SPD data and channel/speed info. Move call to print_dram_info() after cbmem initialization so the SMBIOS data has somewhere to go. Test: build/boot google/swanky, verify via dmidecode. Change-Id: I1c12b539c78d095713421b93115a4095f3d4278d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/soc/intel/baytrail/romstage/raminit.c25
1 files changed, 22 insertions, 3 deletions
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index f1a3c1798b..3ebf8fff2a 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -8,6 +8,7 @@
#include <cbmem.h>
#include <cf9_reset.h>
#include <console/console.h>
+#include <device/dram/ddr3.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/smbus_host.h>
@@ -55,7 +56,23 @@ static void ABI_X86 send_to_console(unsigned char b)
do_putchar(b);
}
-static void print_dram_info(void)
+static void populate_smbios_tables(void *dram_data, int speed, int num_channels)
+{
+ dimm_attr dimm;
+ enum spd_status status;
+
+ /* Decode into dimm_attr struct */
+ status = spd_decode_ddr3(&dimm, *(spd_raw_data *)dram_data);
+
+ /* Some SPDs have bad CRCs, nothing we can do about it */
+ if (status == SPD_STATUS_OK || status == SPD_STATUS_CRC_ERROR) {
+ /* Add table 17 entry for each channel */
+ for (int i = 0; i < num_channels; i++)
+ spd_add_smbios17(i, 0, speed, &dimm);
+ }
+}
+
+static void print_dram_info(void *dram_data)
{
const int mrc_ver_reg = 0xf0;
const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC);
@@ -95,6 +112,8 @@ static void print_dram_info(void)
speed = 1600; break;
}
printk(BIOS_INFO, "%dMHz\n", speed);
+
+ populate_smbios_tables(dram_data, speed, num_channels);
}
void raminit(struct mrc_params *mp, int prev_sleep_state)
@@ -147,8 +166,6 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
ret = mrc_entry(mp);
- print_dram_info();
-
if (prev_sleep_state != ACPI_S3) {
cbmem_initialize_empty();
} else if (cbmem_initialize()) {
@@ -159,6 +176,8 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
#endif
}
+ print_dram_info(mp->mainboard.dram_data[0]);
+
printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret);
printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save,
mp->data_to_save_size);