diff options
| author | Joseph Lo <josephl@nvidia.com> | 2014-03-28 19:13:51 +0800 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-11-14 07:28:09 +0100 |
| commit | 8253bd912ae4cd65ac0aa9ecaebb3aa7efd46cb0 (patch) | |
| tree | 7c1b3e185d25336430257eef9b703092269a8b0d | |
| parent | bab7896e5e04c807bbc3f76d085405c90d247370 (diff) | |
tegra124: fix the dangerous VPR write order
Currently we put the VPR write code just right before the AVP is going
to freeze. We have no idea does the write operation successful or not
before halting the AVP. And the power_on_main_cpu should be the last step
of that. So we make a fix to change the order.
BUG=none
BRANCH=none
TEST=LP0 suspend stress test and check the VPR is correct;
LP0 suspend stress test with video playback
Original-Change-Id: Ia62dde2a020910de39796d1cf62c1bf185cdb372
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/192029
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Original-Commit-Queue: Tom Warren <twarren@nvidia.com>
Original-Tested-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit 51473811fa477cca9ad9cbafdaad4fd4a2309234)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia28329e38fcf12994594b73c805d061804aa01c4
Reviewed-on: http://review.coreboot.org/7459
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
| -rw-r--r-- | src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index b993e31600..0b519d6794 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -583,13 +583,13 @@ void lp0_resume(void) config_tsc(); - power_on_main_cpu(); - // Disable VPR. write32(0, mc_video_protect_size_mb_ptr); write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE, mc_video_protect_reg_ctrl_ptr); + power_on_main_cpu(); + // Halt the AVP. while (1) write32(FLOW_MODE_STOP | EVENT_JTAG, |