diff options
| author | Tim Chu <Tim.Chu@quantatw.com> | 2022-11-01 08:04:33 +0000 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-11-13 15:41:21 +0000 |
| commit | 804c370d742d20a35ffbaf7b1cec219909094f95 (patch) | |
| tree | 3e4ba922edffc45e3b9d5fba6cb6352b46b8df68 | |
| parent | bfad0b0651474d4219e1455026a917081c072ac0 (diff) | |
inc/dev: Add definitions for Link Capability and Slot Capability
Add definitions for Link Capability and Slot Capability and these
definitions may be used in smbios type 9.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Id66710d5569a7247d998cab20c2e41f2e67712cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| -rw-r--r-- | src/include/device/pci_def.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 39369f82ed..59d99051e5 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -422,6 +422,8 @@ #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_MLS 0x000f /* Maximum Link Speed */ +#define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */ #define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */ #define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */ @@ -436,6 +438,7 @@ #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */ +#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ #define PCI_EXP_SLTCTL 24 /* Slot Control */ #define PCI_EXP_SLTSTA 26 /* Slot Status */ #define PCI_EXP_RTCTL 28 /* Root Control */ |