diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-09-22 16:46:16 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-09-25 18:39:06 +0000 |
| commit | 7b523a4be90f6e825d1947bdddc86180f72914c7 (patch) | |
| tree | 03dbe8b4a46808b2e464a8b66e0e4565e267f16f | |
| parent | cdad2ce2b0fb9e3209a681b0231f10e258bbfee0 (diff) | |
soc/intel/alderlake: Use intel_microcode_find() to locate ucode.bin
`intel_microcode_find()` function uses cached ucode data hence it would
avoid locating ucode.bin from CBFS while passing ucode.bin pointer to
FSP.
Change-Id: I8f92c9f20dfb055c19c6996e601c8c24767aecb7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index ec7bff6829..584364b81e 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -3,6 +3,7 @@ #include <assert.h> #include <cbfs.h> #include <console/console.h> +#include <cpu/intel/microcode.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -340,11 +341,12 @@ static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, size_t microcode_len; /* Locate microcode and pass to FSP-S for 2nd microcode loading */ - microcode_file = cbfs_map("cpu_microcode_blob.bin", µcode_len); + microcode_file = intel_microcode_find(); + microcode_len = get_microcode_size(microcode_file); if ((microcode_file != NULL) && (microcode_len != 0)) { /* Update CPU Microcode patch base address/size */ - s_cfg->MicrocodeRegionBase = (uint32_t)microcode_file; + s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file; s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; } |