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authorArthur Heymans <arthur@aheymans.xyz>2019-11-15 19:19:53 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-16 20:39:31 +0000
commit767de0aac753bb67f53d13c48207ade22b094a7e (patch)
treed69dd209f2415e4ffda00086b63f3c97d82c6737
parente5ca52bbba584aa6b654383c06e1b5161f6738d9 (diff)
sb/intel/i82801gx: Only include SPI code with SPI boot devices
On devices lacking SPI boot devices there is a hefty timeout penalty on probing for flash chips and this code would not be useful anyway. Change-Id: I0bec11372ef54c1e1e611b81f7013932257f4ca6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36868 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/southbridge/intel/i82801gx/Kconfig2
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c3
2 files changed, 3 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index 17ee4fcab3..bf9880ac27 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -23,7 +23,7 @@ config SOUTHBRIDGE_INTEL_I82801GX
select COMMON_FADT
select SOUTHBRIDGE_INTEL_COMMON_GPIO
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
- select SOUTHBRIDGE_INTEL_COMMON_SPI
+ select SOUTHBRIDGE_INTEL_COMMON_SPI if BOOT_DEVICE_SPI_FLASH
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select HAVE_INTEL_CHIPSET_LOCKDOWN
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 34250d396f..0330af0060 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -616,7 +616,8 @@ static void lpc_final(struct device *dev)
if (!CONFIG(INTEL_CHIPSET_LOCKDOWN))
return;
- spi_finalize_ops();
+ if (CONFIG(BOOT_DEVICE_SPI_FLASH))
+ spi_finalize_ops();
/* Lock SPIBAR */
SPIBAR16(0) = SPIBAR16(0) | (1 << 15);