AMD Hudson: Enable HD audio

Something about HD audio was scrubbed. Take it back.

Change-Id: I0be96fd103f3ebd4e8c7ef09a184b71aa34ee3fd
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1427
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

9 files changed, 499 insertions, 91 deletions

diff --git a/src/vendorcode/amd/agesa/f15tn/AGESA.h b/src/vendorcode/amd/agesa/f15tn/AGESA.h
index a9e79670ce..fdd02df1ef 100644
--- a/src/vendorcode/amd/agesa/f15tn/AGESA.h
+++ b/src/vendorcode/amd/agesa/f15tn/AGESA.h
@@ -529,9 +529,9 @@ typedef enum {
 
 /// Configuration values for AzaliaController
 typedef enum {
-  hdaconf0  = 0,                         ///< Auto - Detect Azalia controller automatically
-  hdaconf1 ,                          ///< Diable - Disable Azalia controller
-  hdaconf2                             ///< Enable - Enable Azalia controller
+  AzAuto = 0,                         ///< Auto - Detect Azalia controller automatically
+  AzDisable,                          ///< Diable - Disable Azalia controller
+  AzEnable                            ///< Enable - Enable Azalia controller
 } HDA_CONFIG;
 
 /// Configuration values for IrConfig
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h
index ae1e765579..eb169fda50 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h
@@ -130,7 +130,7 @@
       extern FCH_TASK_ENTRY    FchInitEnvIde;
       extern FCH_TASK_ENTRY    FchInitEnvSd;
       extern FCH_TASK_ENTRY    FchInitEnvIr;
-      extern FCH_TASK_ENTRY    Fchdef178 ;
+      extern FCH_TASK_ENTRY    FchInitEnvAzalia;
       extern FCH_TASK_ENTRY    FchInitEnvHwm;
       extern FCH_TASK_ENTRY    FchInitEnvImc;
     #endif
@@ -139,6 +139,7 @@
   #ifdef AGESA_ENTRY_INIT_MID
     #if AGESA_ENTRY_INIT_MID == TRUE
       extern FCH_TASK_ENTRY    FchInitMidHwm;
+      extern FCH_TASK_ENTRY    FchInitMidAzalia;
       extern FCH_TASK_ENTRY    FchInitMidGec;
       extern FCH_TASK_ENTRY    FchInitMidSata;
       extern FCH_TASK_ENTRY    FchInitMidIde;
@@ -167,6 +168,7 @@
       extern FCH_TASK_ENTRY    FchInitLateUsbOhci;
       extern FCH_TASK_ENTRY    FchInitLateUsbXhci;
       extern FCH_TASK_ENTRY    FchInitLateImc;
+      extern FCH_TASK_ENTRY    FchInitLateAzalia;
       extern FCH_TASK_ENTRY    FchInitLateHwm;
     #endif
   #endif
@@ -247,6 +249,7 @@
   #undef  FCH_NO_IMC_SUPPORT
   #undef  FCH_NO_SD_SUPPORT
   #undef  FCH_NO_IR_SUPPORT
+  #undef  FCH_NO_AZALIA_SUPPORT
   #undef  FCH_NO_HWM_SUPPORT
 
   #define FCH_NO_GEC_SUPPORT        TRUE
@@ -504,6 +507,19 @@
     #define InstallFchInitLateIr        &FchTaskDummy
   #endif
 
+  #ifndef FCH_NO_AZALIA_SUPPORT
+    #define BLOCK_AZALIA_SIZE           sizeof (FCH_AZALIA)
+    #define InstallFchInitResetAzalia   &FchInitResetAzalia
+    #define InstallFchInitEnvAzalia     &FchInitEnvAzalia
+    #define InstallFchInitMidAzalia     &FchInitMidAzalia
+    #define InstallFchInitLateAzalia    &FchInitLateAzalia
+  #else
+    #define BLOCK_AZALIA_SIZE           0
+    #define InstallFchInitResetAzalia   &FchTaskDummy
+    #define InstallFchInitEnvAzalia     &FchTaskDummy
+    #define InstallFchInitMidAzalia     &FchTaskDummy
+    #define InstallFchInitLateAzalia    &FchTaskDummy
+  #endif
 
   #ifndef FCH_NO_HWM_SUPPORT
     #define BLOCK_HWM_SIZE              sizeof (FCH_HWM)
@@ -618,6 +634,11 @@
     #define CFG_HPET_BASE_ADDRESS           DFLT_HPET_BASE_ADDRESS
   #endif
 
+  #ifdef BLDCFG_AZALIA_SSID
+    #define CFG_AZALIA_SSID                 BLDCFG_AZALIA_SSID
+  #else
+    #define CFG_AZALIA_SSID                 DFLT_AZALIA_SSID
+  #endif
 
   #ifdef BLDCFG_SMBUS_SSID
     #define CFG_SMBUS_SSID                  BLDCFG_SMBUS_SSID
@@ -836,7 +857,7 @@
         InstallFchInitEnvSata,
         InstallFchInitEnvIde,
         InstallFchInitEnvGec,
-        Fchdef178 ,
+        InstallFchInitEnvAzalia,
         InstallFchInitEnvAb,
         InstallFchInitEnvHwm,
         InstallFchInitEnvGppPhaseII,
@@ -861,6 +882,7 @@
         InstallFchInitMidSata,
         InstallFchInitMidIde,
         InstallFchInitMidGec,
+        InstallFchInitMidAzalia,
         InstallFchInitMidHwm,
         NULL
       };
@@ -883,6 +905,7 @@
         InstallFchInitLateSata,
         InstallFchInitLateIde,
         InstallFchInitLateGec,
+        &FchTaskDummy,
         InstallFchInitLateImc,
         InstallFchInitLateHwm,
         InstallFchInitLateGpp,
@@ -911,7 +934,7 @@
         InstallFchInitEnvSata,
         InstallFchInitEnvIde,
         InstallFchInitEnvGec,
-        Fchdef178 ,
+        InstallFchInitEnvAzalia,
         InstallFchInitEnvAb,
         InstallFchInitEnvGppPhaseII,
         InstallFchInitEnvAbS,
@@ -936,6 +959,7 @@
         InstallFchInitMidSata,
         InstallFchInitMidIde,
         InstallFchInitMidGec,
+        InstallFchInitMidAzalia,
         InstallFchInitLateSata,
         InstallFchInitLateIde,
         InstallFchInitLateHwAcpi,
@@ -977,6 +1001,7 @@
   #define CFG_SMI_CMD_PORT_ADDRESS           0
   #define CFG_ACPI_PMA_CNTBLK_ADDRESS        0
   #define CFG_GEC_SHADOW_ROM_BASE            0
+  #define CFG_AZALIA_SSID                    0
   #define CFG_SMBUS_SSID                     0
   #define CFG_IDE_SSID                       0
   #define CFG_SATA_AHCI_SSID                 0
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaEnv.c
index cf5bfc6576..640492a92d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaEnv.c
@@ -84,7 +84,7 @@
  *
  */
 VOID
-Fchdef178  (
+FchInitEnvAzalia (
   IN  VOID     *FchDataPtr
   )
 {
@@ -94,15 +94,15 @@ Fchdef178  (
   LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
   StdHeader = LocalCfgPtr->StdHeader;
 
-  if ( LocalCfgPtr->Azalia.AzaliaEnable == hdaconf1  ) {
+  if ( LocalCfgPtr->Azalia.AzaliaEnable == AzDisable  ) {
     RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEB , AccessWidth8, (UINT32)~BIT0, 0);
   } else {
     RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEB , AccessWidth8, (UINT32)~BIT0, BIT0);
-    RwPci ((((0x14<<3)+2)  << 16) + FCH_AZ_REG4C, AccessWidth8, (UINT32)~BIT0, BIT0, StdHeader);
+    RwPci ((((0x14<<3)+2)  << 16) + 0x4C, AccessWidth8, (UINT32)~BIT0, BIT0, StdHeader);
 
     if ( LocalCfgPtr->Azalia.AzaliaMsiEnable) {
-      RwPci ((((0x14<<3)+2)  << 16) + FCH_AZ_REG44, AccessWidth32, (UINT32)~BIT8, BIT8, StdHeader);
-      RwPci ((((0x14<<3)+2)  << 16) + FCH_AZ_REG60, AccessWidth32, (UINT32)~BIT16, BIT16, StdHeader);
+      RwPci ((((0x14<<3)+2)  << 16) + 0x44, AccessWidth32, (UINT32)~BIT8, BIT8, StdHeader);
+      RwPci ((((0x14<<3)+2)  << 16) + 0x60, AccessWidth32, (UINT32)~BIT16, BIT16, StdHeader);
     }
   }
 }
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaLate.c
index 37acfc65f8..f3e67a84ed 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaLate.c
@@ -78,7 +78,7 @@
  *
  */
 VOID
-Fchdef180  (
+FchInitLateAzalia  (
   IN  VOID     *FchDataPtr
   )
 {
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaMid.c
index 65c5e5928a..4dfba964c9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaMid.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaMid.c
@@ -74,10 +74,465 @@
 // Declaration of local functions
 //
 
+VOID
+ConfigureAzaliaPinCmd (
+  IN FCH_DATA_BLOCK  *FchDataPtr,
+  IN UINT32 BAR0,
+  IN UINT8 ChannelNum
+  );
 
+VOID
+ConfigureAzaliaSetConfigD4Dword (
+  IN CODEC_ENTRY  *TempAzaliaCodecEntryPtr,
+  IN UINT32 ChannelNumDword,
+  IN UINT32 BAR0,
+  IN AMD_CONFIG_PARAMS *StdHeader
+  );
 
+/**
+ * FchInitMidAzalia - Config Azalia controller after PCI
+ * emulation
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+FchInitMidAzalia (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8        Index;
+  BOOLEAN      EnableAzalia;
+  UINT32       PinRouting;
+  UINT8        ChannelNum;
+  UINT8        AzaliaTempVariableByte;
+  UINT16       AzaliaTempVariableWord;
+  UINT32       BAR0;
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  EnableAzalia = FALSE;
+  ChannelNum = 0;
+  AzaliaTempVariableByte = 0;
+  AzaliaTempVariableWord = 0;
+  BAR0 = 0;
+
+  if ( LocalCfgPtr->Azalia.AzaliaEnable == AzDisable) {
+    return;
+  } else {
+    RwPci ((((0x14<<3)+2) << 16) + 0x04, AccessWidth8, (UINT32)~BIT1, (UINT32)BIT1, StdHeader);
+
+    if ( LocalCfgPtr->Azalia.AzaliaSsid != 0 ) {
+      RwPci ((((0x14<<3)+2) << 16) + 0x2C, AccessWidth32, 0x00, LocalCfgPtr->Azalia.AzaliaSsid, StdHeader);
+    }
+
+    ReadPci ((((0x14<<3)+2)  << 16) + 0x10, AccessWidth32, &BAR0, StdHeader);
+
+    if ( BAR0 != 0 ) {
+      if ( BAR0 != 0xFFFFFFFF ) {
+        BAR0 &=  ~(0x03FFF);
+        EnableAzalia = TRUE;
+      }
+    }
+  }
+
+  if ( EnableAzalia ) {
+    //
+    // Get SDIN Configuration
+    //
+    if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin0 == 2 ) {
+      RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG167, AccessWidth8, 0, 0x3E);
+      RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG167, AccessWidth8, 0, 0x00);
+    } else {
+      RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG167, AccessWidth8, 0, 0x0);
+      RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG167, AccessWidth8, 0, 0x01);
+    }
+
+    if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin1 == 2 ) {
+      RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG168, AccessWidth8, 0, 0x3E);
+      RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG168, AccessWidth8, 0, 0x00);
+    } else {
+      RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG168, AccessWidth8, 0, 0x0);
+      RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG168, AccessWidth8, 0, 0x01);
+    }
+
+    if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin2 == 2 ) {
+      RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG169, AccessWidth8, 0, 0x3E);
+      RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG169, AccessWidth8, 0, 0x00);
+    } else {
+      RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG169, AccessWidth8, 0, 0x0);
+      RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG169, AccessWidth8, 0, 0x01);
+    }
+
+    if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin3 == 2 ) {
+      RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG170, AccessWidth8, 0, 0x3E);
+      RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG170, AccessWidth8, 0, 0x00);
+    } else {
+      RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG170, AccessWidth8, 0, 0x0);
+      RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG170, AccessWidth8, 0, 0x01);
+    }
+
+    Index = 11;
+    do {
+      ReadMem ( BAR0 + 0x08, AccessWidth8, &AzaliaTempVariableByte);
+      AzaliaTempVariableByte |= BIT0;
+      WriteMem (BAR0 + 0x08, AccessWidth8, &AzaliaTempVariableByte);
+      FchStall (1000, StdHeader);
+      ReadMem (BAR0 + 0x08, AccessWidth8, &AzaliaTempVariableByte);
+      Index--;
+    }  while ((! (AzaliaTempVariableByte & BIT0)) && (Index > 0) );
+
+    if ( Index == 0 ) {
+      return;
+    }
+
+    FchStall (1000, StdHeader);
+    ReadMem ( BAR0 + 0x0E, AccessWidth16, &AzaliaTempVariableWord);
+    if ( AzaliaTempVariableWord & 0x0F ) {
+
+      //
+      //at least one azalia codec found
+      //
+      //PinRouting = LocalCfgPtr->Azalia.AZALIA_CONFIG.AzaliaSdinPin;
+      //new structure need make up PinRouting
+      //need adjust later!!!
+      //
+      PinRouting = 0;
+      PinRouting = (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin3;
+      PinRouting <<= 8;
+      PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin2;
+      PinRouting <<= 8;
+      PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin1;
+      PinRouting <<= 8;
+      PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin0;
+
+      do {
+        if ( ( ! (PinRouting & BIT0) ) && (PinRouting & BIT1) ) {
+          ConfigureAzaliaPinCmd (LocalCfgPtr, BAR0, ChannelNum);
+        }
+        PinRouting >>= 8;
+        ChannelNum++;
+      }  while ( ChannelNum != 4 );
+    } else {
+      //
+      //No Azalia codec found
+      //
+      if ( LocalCfgPtr->Azalia.AzaliaEnable != AzEnable ) {
+        EnableAzalia = FALSE;                      ///set flag to disable Azalia
+      }
+    }
+  }
+
+  if ( EnableAzalia ) {
+    if ( LocalCfgPtr->Azalia.AzaliaSnoop == 1 ) {
+      RwPci ((((0x14<<3)+2)  << 16) + 0x42, AccessWidth8, 0xFF, BIT1 + BIT0, StdHeader);
+    }
+  } else {
+    //
+    //disable Azalia controller
+    //
+    RwPci ((((0x14<<3)+2)  << 16) + 0x04, AccessWidth16, 0, 0, StdHeader);
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEB , AccessWidth8, (UINT32)~BIT0, 0);
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEB , AccessWidth8, (UINT32)~BIT0, 0);
+  }
+}
+
+/**
+ * Pin Config for ALC880, ALC882 and ALC883.
+ *
+ *
+ *
+ */
+CODEC_ENTRY AzaliaCodecAlc882Table[] =
+{
+  {0x14, 0x01014010},
+  {0x15, 0x01011012},
+  {0x16, 0x01016011},
+  {0x17, 0x01012014},
+  {0x18, 0x01A19030},
+  {0x19, 0x411111F0},
+  {0x1a, 0x01813080},
+  {0x1b, 0x411111F0},
+  {0x1C, 0x411111F0},
+  {0x1d, 0x411111F0},
+  {0x1e, 0x01441150},
+  {0x1f, 0x01C46160},
+  {0xff, 0xffffffff}
+};
+
+/**
+ * Pin Config for ALC0262.
+ *
+ *
+ *
+ */
+CODEC_ENTRY AzaliaCodecAlc262Table[] =
+{
+  {0x14, 0x01014010},
+  {0x15, 0x411111F0},
+  {0x16, 0x411111F0},
+  {0x18, 0x01A19830},
+  {0x19, 0x02A19C40},
+  {0x1a, 0x01813031},
+  {0x1b, 0x02014C20},
+  {0x1c, 0x411111F0},
+  {0x1d, 0x411111F0},
+  {0x1e, 0x0144111E},
+  {0x1f, 0x01C46150},
+  {0xff, 0xffffffff}
+};
+
+/**
+ * Pin Config for ALC0269.
+ *
+ *
+ *
+ */
+CODEC_ENTRY AzaliaCodecAlc269Table[] =
+{
+  {0x12, 0x99A308F0},
+  {0x14, 0x99130010},
+  {0x15, 0x0121101F},
+  {0x16, 0x99036120},
+  {0x18, 0x01A19850},
+  {0x19, 0x99A309F0},
+  {0x1a, 0x01813051},
+  {0x1b, 0x0181405F},
+  {0x1d, 0x40134601},
+  {0x1e, 0x01442130},
+  {0x11, 0x99430140},
+  {0x20, 0x0030FFFF},
+  {0xff, 0xffffffff}
+};
+
+/**
+ * Pin Config for ALC0861.
+ *
+ *
+ *
+ */
+CODEC_ENTRY AzaliaCodecAlc861Table[] =
+{
+  {0x01, 0x8086C601},
+  {0x0B, 0x01014110},
+  {0x0C, 0x01813140},
+  {0x0D, 0x01A19941},
+  {0x0E, 0x411111F0},
+  {0x0F, 0x02214420},
+  {0x10, 0x02A1994E},
+  {0x11, 0x99330142},
+  {0x12, 0x01451130},
+  {0x1F, 0x411111F0},
+  {0x20, 0x411111F0},
+  {0x23, 0x411111F0},
+  {0xff, 0xffffffff}
+};
+
+/**
+ * Pin Config for ALC0889.
+ *
+ *
+ *
+ */
+CODEC_ENTRY AzaliaCodecAlc889Table[] =
+{
+  {0x11, 0x411111F0},
+  {0x14, 0x01014010},
+  {0x15, 0x01011012},
+  {0x16, 0x01016011},
+  {0x17, 0x01013014},
+  {0x18, 0x01A19030},
+  {0x19, 0x411111F0},
+  {0x1a, 0x411111F0},
+  {0x1b, 0x411111F0},
+  {0x1C, 0x411111F0},
+  {0x1d, 0x411111F0},
+  {0x1e, 0x01442150},
+  {0x1f, 0x01C42160},
+  {0xff, 0xffffffff}
+};
+
+/**
+ * Pin Config for ADI1984.
+ *
+ *
+ *
+ */
+CODEC_ENTRY AzaliaCodecAd1984Table[] =
+{
+  {0x11, 0x0221401F},
+  {0x12, 0x90170110},
+  {0x13, 0x511301F0},
+  {0x14, 0x02A15020},
+  {0x15, 0x50A301F0},
+  {0x16, 0x593301F0},
+  {0x17, 0x55A601F0},
+  {0x18, 0x55A601F0},
+  {0x1A, 0x91F311F0},
+  {0x1B, 0x014511A0},
+  {0x1C, 0x599301F0},
+  {0xff, 0xffffffff}
+};
+
+/**
+ * FrontPanel Config table list
+ *
+ *
+ *
+ */
+CODEC_ENTRY FrontPanelAzaliaCodecTableList[] =
+{
+  {0x19, 0x02A19040},
+  {0x1b, 0x02214020},
+  {0xff, 0xffffffff}
+};
+
+/**
+ * Current HD Audio support codec list
+ *
+ *
+ *
+ */
+CODEC_TBL_LIST AzaliaCodecTableList[] =
+{
+  {0x010ec0880, &AzaliaCodecAlc882Table[0]},
+  {0x010ec0882, &AzaliaCodecAlc882Table[0]},
+  {0x010ec0883, &AzaliaCodecAlc882Table[0]},
+  {0x010ec0885, &AzaliaCodecAlc882Table[0]},
+  {0x010ec0889, &AzaliaCodecAlc889Table[0]},
+  {0x010ec0262, &AzaliaCodecAlc262Table[0]},
+  {0x010ec0269, &AzaliaCodecAlc269Table[0]},
+  {0x010ec0861, &AzaliaCodecAlc861Table[0]},
+  {0x011d41984, &AzaliaCodecAd1984Table[0]},
+  { (UINT32) 0x0FFFFFFFF, (CODEC_ENTRY*) (UINTN)0x0FFFFFFFF}
+};
+
+/**
+ * ConfigureAzaliaPinCmd - Configuration HD Audio PIN Command
+ *
+ *
+ * @param[in] FchDataPtr              Fch configuration structure pointer.
+ * @param[in] BAR0               HD Audio BAR0 base address.
+ * @param[in] ChannelNum         Channel Number.
+ *
+ */
+VOID
+ConfigureAzaliaPinCmd (
+  IN  FCH_DATA_BLOCK     *FchDataPtr,
+  IN  UINT32         BAR0,
+  IN  UINT8          ChannelNum
+  )
+{
+  UINT32           AzaliaTempVariable;
+  UINT32           ChannelNumDword;
+  CODEC_TBL_LIST   *TempAzaliaOemCodecTablePtr;
+  CODEC_ENTRY      *TempAzaliaCodecEntryPtr;
+
+  if ( (FchDataPtr->Azalia.AzaliaPinCfg) != 1 ) {
+    return;
+  }
+
+  ChannelNumDword = ChannelNum << 28;
+  AzaliaTempVariable = 0xF0000;
+  AzaliaTempVariable |= ChannelNumDword;
+
+  WriteMem (BAR0 + 0x60, AccessWidth32, &AzaliaTempVariable);
+  FchStall (600, FchDataPtr->StdHeader);
+  ReadMem (BAR0 + 0x64, AccessWidth32, &AzaliaTempVariable);
+
+  if ( ((FchDataPtr->Azalia.AzaliaOemCodecTablePtr) == NULL) || ((FchDataPtr->Azalia.AzaliaOemCodecTablePtr) == ((CODEC_TBL_LIST*) (UINTN)0xFFFFFFFF))) {
+    TempAzaliaOemCodecTablePtr = (CODEC_TBL_LIST*) (&AzaliaCodecTableList[0]);
+  } else {
+    TempAzaliaOemCodecTablePtr = (CODEC_TBL_LIST*) FchDataPtr->Azalia.AzaliaOemCodecTablePtr;
+  }
+
+  while ( TempAzaliaOemCodecTablePtr->CodecId != 0xFFFFFFFF ) {
+    if ( TempAzaliaOemCodecTablePtr->CodecId == AzaliaTempVariable ) {
+      break;
+    } else {
+      ++TempAzaliaOemCodecTablePtr;
+    }
+  }
+
+  if ( TempAzaliaOemCodecTablePtr->CodecId != 0xFFFFFFFF ) {
+    TempAzaliaCodecEntryPtr = (CODEC_ENTRY*) TempAzaliaOemCodecTablePtr->CodecTablePtr;
+    if ( ((FchDataPtr->Azalia.AzaliaOemCodecTablePtr) == NULL) || ((FchDataPtr->Azalia.AzaliaOemCodecTablePtr) == ((CODEC_TBL_LIST*) (UINTN)0xFFFFFFFF)) ) {
+      TempAzaliaCodecEntryPtr = (CODEC_ENTRY*) (TempAzaliaCodecEntryPtr);
+    }
+
+    ConfigureAzaliaSetConfigD4Dword (TempAzaliaCodecEntryPtr, ChannelNumDword, BAR0, FchDataPtr->StdHeader);
+
+    if ( FchDataPtr->Azalia.AzaliaFrontPanel != 1 ) {
+      if ( (FchDataPtr->Azalia.AzaliaFrontPanel == 2) || (FchDataPtr->Azalia.FrontPanelDetected == 1) ) {
+        if ( ((FchDataPtr->Azalia.AzaliaOemFpCodecTablePtr) == NULL) || ((FchDataPtr->Azalia.AzaliaOemFpCodecTablePtr) == (VOID*) (UINTN)0xFFFFFFFF) ) {
+          TempAzaliaCodecEntryPtr = (CODEC_ENTRY*) (&FrontPanelAzaliaCodecTableList[0]);
+        } else {
+          TempAzaliaCodecEntryPtr = (CODEC_ENTRY*) FchDataPtr->Azalia.AzaliaOemFpCodecTablePtr;
+        }
+
+        ConfigureAzaliaSetConfigD4Dword (TempAzaliaCodecEntryPtr, ChannelNumDword, BAR0, FchDataPtr->StdHeader);
+      }
+    }
+  }
+}
+
+/**
+ * ConfigureAzaliaSetConfigD4Dword - Configuration HD Audio Codec table
+ *
+ *
+ * @param[in] TempAzaliaCodecEntryPtr    HD Audio Codec table structure pointer.
+ * @param[in] ChannelNumDword               HD Audio Channel Number.
+ * @param[in] BAR0                     HD Audio BAR0 base address.
+ * @param[in] StdHeader
+ *
+ */
+VOID
+ConfigureAzaliaSetConfigD4Dword (
+  IN  CODEC_ENTRY     *TempAzaliaCodecEntryPtr,
+  IN  UINT32          ChannelNumDword,
+  IN  UINT32          BAR0,
+  IN  AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8    TempByte1;
+  UINT8    TempByte2;
+  UINT8    Index;
+  UINT32   TempDword1;
+  UINT32   TempDword2;
+
+  TempDword1 = 0;
+  TempDword2 = 0;
+
+  while ( (TempAzaliaCodecEntryPtr->Nid) != 0xFF ) {
+    TempByte1 = 0x20;
+    if ( (TempAzaliaCodecEntryPtr->Nid) == 0x1 ) {
+      TempByte1 = 0x24;
+    }
+
+    TempDword1 =  TempAzaliaCodecEntryPtr->Nid;
+    TempDword1 &= 0xff;
+    TempDword1 <<= 20;
+    TempDword1 |= ChannelNumDword;
+    TempDword1 |= (0x700 << 8);
 
+    for ( Index = 4; Index > 0; Index-- ) {
+      do {
+        ReadMem (BAR0 + 0x68, AccessWidth32, &TempDword2);
+      } while ( (TempDword2 & BIT0) != 0 );
 
+      TempByte2 = (UINT8) (( (TempAzaliaCodecEntryPtr->Byte40) >> ((4 - Index) * 8 ) ) & 0xff);
+      TempDword1 =  (TempDword1 & 0xFFFF0000) + ((TempByte1 - Index) << 8) + TempByte2;
+      WriteMem (BAR0 + 0x60, AccessWidth32, &TempDword1);
+      FchStall (60, StdHeader);
+    }
 
+    ++TempAzaliaCodecEntryPtr;
+  }
+}
 
 
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaReset.c
index d10857e8a8..7c7855e619 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaReset.c
@@ -80,7 +80,7 @@
  *
  */
 VOID
-Fchdef174  (
+FchInitResetAzalia  (
   IN  VOID     *FchDataPtr
   )
 {
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h
index af1d1ba1b1..f8519ee321 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h
@@ -170,13 +170,13 @@ UINT32 GppGetFchTempBus (IN AMD_CONFIG_PARAMS *StdHeader);
 ///
 ///  Pei Phase
 ///
-VOID  Fchdef174     (IN VOID  *FchDataPtr);
+VOID  FchInitResetAzalia     (IN VOID  *FchDataPtr);
 ///
 ///  Dxe Phase
 ///
-VOID  Fchdef178       (IN VOID  *FchDataPtr);
-VOID  Fchdef179       (IN VOID  *FchDataPtr);
-VOID  Fchdef180      (IN VOID  *FchDataPtr);
+VOID  FchInitEnvAzalia      (IN VOID  *FchDataPtr);
+VOID  FchInitMidAzalia      (IN VOID  *FchDataPtr);
+VOID  FchInitLateAzalia     (IN VOID  *FchDataPtr);
 
 
 ///
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h
index 963d96da66..6b15aaf38b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h
@@ -892,78 +892,6 @@
 //  Device 20 (0x14) Func 2
 //
 
-#define FCH_AZ_REG00             0x00        // Vendor ID - R
-#define FCH_AZ_REG02             0x02        // Device ID - R/W
-#define FCH_AZ_REG04             0x04        // PCI Command
-#define FCH_AZ_REG06             0x06        // PCI Status - R/W
-#define FCH_AZ_REG08             0x08        // Revision ID
-#define FCH_AZ_REG09             0x09        // Programming Interface
-#define FCH_AZ_REG0A             0x0A        // Sub Class Code
-#define FCH_AZ_REG0B             0x0B        // Base Class Code
-#define FCH_AZ_REG0C             0x0C        // Cache Line Size - R/W
-#define FCH_AZ_REG0D             0x0D        // Latency Timer
-#define FCH_AZ_REG0E             0x0E        // Header Type
-#define FCH_AZ_REG0F             0x0F        // BIST
-#define FCH_AZ_REG10             0x10        // Lower Base Address Register
-#define FCH_AZ_REG14             0x14        // Upper Base Address Register
-#define FCH_AZ_REG2C             0x2C        // Subsystem Vendor ID
-#define FCH_AZ_REG2D             0x2D        // Subsystem ID
-#define FCH_AZ_REG34             0x34        // Capabilities Pointer
-#define FCH_AZ_REG3C             0x3C        // Interrupt Line
-#define FCH_AZ_REG3D             0x3D        // Interrupt Pin
-#define FCH_AZ_REG3E             0x3E        // Minimum Grant
-#define FCH_AZ_REG3F             0x3F        // Maximum Latency
-#define FCH_AZ_REG40             0x40        // Misc Control 1
-#define FCH_AZ_REG42             0x42        // Misc Control 2 Register
-#define FCH_AZ_REG43             0x43        // Misc Control 3 Register
-#define FCH_AZ_REG44             0x44        // Interrupt Pin Control Register
-#define FCH_AZ_REG46             0x46        // Debug Control Register
-#define FCH_AZ_REG4C             0x4C
-#define FCH_AZ_REG50             0x50        // Power Management Capability ID
-#define FCH_AZ_REG52             0x52        // Power Management Capabilities
-#define FCH_AZ_REG54             0x54        // Power Management Control/Status
-#define FCH_AZ_REG60             0x60        // MSI Capability ID
-#define FCH_AZ_REG62             0x62        // MSI Message Control
-#define FCH_AZ_REG64             0x64        // MSI Message Lower Address
-#define FCH_AZ_REG68             0x68        // MSI Message Upper Address
-#define FCH_AZ_REG6C             0x6C        // MSI Message Data
-
-#define FCH_AZ_BAR_REG00         0x00        // Global Capabilities - R
-#define FCH_AZ_BAR_REG02         0x02        // Minor Version - R
-#define FCH_AZ_BAR_REG03         0x03        // Major Version - R
-#define FCH_AZ_BAR_REG04         0x04        // Output Payload Capability - R
-#define FCH_AZ_BAR_REG06         0x06        // Input Payload Capability - R
-#define FCH_AZ_BAR_REG08         0x08        // Global Control - R/W
-#define FCH_AZ_BAR_REG0C         0x0C        // Wake Enable - R/W
-#define FCH_AZ_BAR_REG0E         0x0E        // State Change Status - R/W
-#define FCH_AZ_BAR_REG10         0x10        // Global Status - R/W
-#define FCH_AZ_BAR_REG18         0x18        // Output Stream Payload Capability - R
-#define FCH_AZ_BAR_REG1A         0x1A        // Input Stream Payload Capability - R
-#define FCH_AZ_BAR_REG20         0x20        // Interrupt Control - R/W
-#define FCH_AZ_BAR_REG24         0x24        // Interrupt Status - R/W
-#define FCH_AZ_BAR_REG30         0x30        // Wall Clock Counter - R
-#define FCH_AZ_BAR_REG38         0x38        // Stream Synchronization - R/W
-#define FCH_AZ_BAR_REG40         0x40        // CORB Lower Base Address - R/W
-#define FCH_AZ_BAR_REG44         0x44        // CORB Upper Base Address - RW
-#define FCH_AZ_BAR_REG48         0x48        // CORB Write Pointer - R/W
-#define FCH_AZ_BAR_REG4A         0x4A        // CORB Read Pointer - R/W
-#define FCH_AZ_BAR_REG4C         0x4C        // CORB Control - R/W
-#define FCH_AZ_BAR_REG4D         0x4D        // CORB Status - R/W
-#define FCH_AZ_BAR_REG4E         0x4E        // CORB Size - R/W
-#define FCH_AZ_BAR_REG50         0x50        // RIRB Lower Base Address - RW
-#define FCH_AZ_BAR_REG54         0x54        // RIRB Upper Address - RW
-#define FCH_AZ_BAR_REG58         0x58        // RIRB Write Pointer - RW
-#define FCH_AZ_BAR_REG5A         0x5A        // RIRB Response Interrupt Count - R/W
-#define FCH_AZ_BAR_REG5C         0x5C        // RIRB Control - R/W
-#define FCH_AZ_BAR_REG5D         0x5D        // RIRB Status - R/W
-#define FCH_AZ_BAR_REG5E         0x5E        // RIRB Size - R/W
-#define FCH_AZ_BAR_REG60         0x60        // Immediate Command Output Interface - R/W
-#define FCH_AZ_BAR_REG64         0x64        // Immediate Command Input Interface - R/W
-#define FCH_AZ_BAR_REG68         0x68        // Immediate Command Input Interface - R/W
-#define FCH_AZ_BAR_REG70         0x70        // DMA Position Lower Base Address - R/W
-#define FCH_AZ_BAR_REG74         0x74        // DMA Position Upper Base Address - R/W
-#define FCH_AZ_BAR_REG2030       0x2030      // Wall Clock Counter Alias - R
-
 //
 //  FCH LPC Device  0x780E
 //  Device 20 (0x14) Func 3
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c
index f9c29d9789..b1964c8231 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c
@@ -89,7 +89,7 @@
  */
 CONST FCH_INTERFACE ROMDATA FchInterfaceDefault = {
   SdAmda,              // SdConfig
-  hdaconf2 ,            // AzaliaControl
+  AzEnable,            // AzaliaControl
   IrRxTx0Tx1,          // IrConfig
   TRUE,                // UmiGen2
   SataAhci,            // SataClass
@@ -273,7 +273,7 @@ FCH_DATA_BLOCK   InitEnvCfgDefault = {
   },
 
   {                          // FCH_AZALIA
-    hdaconf2,               // AzaliaEnable
+    AzEnable,               // AzaliaEnable
     FALSE,                   // AzaliaMsiEnable
     0x00000000,              // AzaliaSsid
     1,                       // AzaliaPinCfg