soc/intel/meteorlake: Use double digit GPIO pad numbers

Google uses two digit GPIO pad numbers for internal GPIO references
and Intel has updated their GPIO naming schemes too (see the GPIO
implementation worksheet #641238) so use double digit GPIO pad numbers.
Format -
"GPP_%c%02d", gpio_group, gpio_pad_num

e.g.
GPP_A0 -> GPP_A00,
GPP_V2 -> GPP_V02,
GPP_C9 -> GPP_C09 etc.

BUG=b:238196741
TEST=Able to build meteorlake based google/rex.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ieb7569c1a35b08c0970a604ec7b4b91e6179dd28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65719
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

4 files changed, 229 insertions, 229 deletions

diff --git a/src/mainboard/google/rex/variants/baseboard/rex/gpio.c b/src/mainboard/google/rex/variants/baseboard/rex/gpio.c
index 70f05c49b1..8ddd6cece0 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/gpio.c
+++ b/src/mainboard/google/rex/variants/baseboard/rex/gpio.c
@@ -7,19 +7,19 @@
 /* Pad configuration in ramstage */
 static const struct pad_config gpio_table[] = {
 	/* ToDo: Fill gpio configuration */
-	/* H8 : UART0_RXD ==> UART_DBG_TX_SOC_RX */
-	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
-	/* H9 : UART0_TXD ==> UART_DBG_RX_SOC_TX */
-	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	/* H08 : UART0_RXD ==> UART_DBG_TX_SOC_RX */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* H09 : UART0_TXD ==> UART_DBG_RX_SOC_TX */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
 };
 
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
 	/* ToDo: Fill early gpio configuration */
-	/* H8 : UART0_RXD ==> UART_DBG_TX_SOC_RX */
-	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
-	/* H9 : UART0_TXD ==> UART_DBG_RX_SOC_TX */
-	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	/* H08 : UART0_RXD ==> UART_DBG_TX_SOC_RX */
+	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+	/* H09 : UART0_TXD ==> UART_DBG_RX_SOC_TX */
+	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
 };
 
 const struct pad_config *__weak variant_gpio_table(size_t *num)
diff --git a/src/soc/intel/meteorlake/gpio.c b/src/soc/intel/meteorlake/gpio.c
index 85b04f35e5..83c6d840ba 100644
--- a/src/soc/intel/meteorlake/gpio.c
+++ b/src/soc/intel/meteorlake/gpio.c
@@ -31,50 +31,50 @@ static const struct reset_mapping rst_map_com3[] = {
  */
 static const struct pad_group mtl_community0_groups[] = {
 	INTEL_GPP(GPP_PECI, GPP_PECI, GPP_VIDALERT_B),			/* GPP_CPU */
-	INTEL_GPP_BASE(GPP_PECI, GPP_V0, GPP_V23, 0),			/* GPP_V */
-	INTEL_GPP_BASE(GPP_PECI, GPP_C0, GPP_C23, 32),			/* GPP_C */
+	INTEL_GPP_BASE(GPP_PECI, GPP_V00, GPP_V23, 0),			/* GPP_V */
+	INTEL_GPP_BASE(GPP_PECI, GPP_C00, GPP_C23, 32),			/* GPP_C */
 };
 
 static const struct vw_entries mtl_community0_vw[] = {
-	{GPP_C0, GPP_C23},
+	{GPP_C00, GPP_C23},
 };
 
 static const struct pad_group mtl_community1_groups[] = {
-	INTEL_GPP_BASE(GPP_A0, GPP_A0, GPP_ESPI_CLK_LPBK, 64),		/* GPP_A */
-	INTEL_GPP_BASE(GPP_A0, GPP_E0, GPP_THC0_GSPI_CLK_LPBK, 96),	/* GPP_E */
+	INTEL_GPP_BASE(GPP_A00, GPP_A00, GPP_ESPI_CLK_LPBK, 64),		/* GPP_A */
+	INTEL_GPP_BASE(GPP_A00, GPP_E00, GPP_THC0_GSPI_CLK_LPBK, 96),	/* GPP_E */
 };
 
 static const struct vw_entries mtl_community1_vw[] = {
-	{GPP_A0, GPP_A20},
-	{GPP_E0, GPP_E23},
+	{GPP_A00, GPP_A20},
+	{GPP_E00, GPP_E23},
 };
 
 static const struct pad_group mtl_community3_groups[] = {
-	INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_LPI3C0_CLK_LPBK, 128),	/* GPP_H */
-	INTEL_GPP_BASE(GPP_H0, GPP_F0, GPP_GSPI0A_CLK_LOOPBK, 160),	/* GPP_F */
-	INTEL_GPP(GPP_H0, GPP_SPI0_IO_2, GPP_SPI0_CLK_LOOPBK),		/* GPP_SPI0 */
-	INTEL_GPP(GPP_H0, GPP_VGPIO3_USB0, GPP_VGPIO3_THC3),		/* GPP_VGPIO3 */
+	INTEL_GPP_BASE(GPP_H00, GPP_H00, GPP_LPI3C0_CLK_LPBK, 128),	/* GPP_H */
+	INTEL_GPP_BASE(GPP_H00, GPP_F00, GPP_GSPI0A_CLK_LOOPBK, 160),	/* GPP_F */
+	INTEL_GPP(GPP_H00, GPP_SPI0_IO_2, GPP_SPI0_CLK_LOOPBK),		/* GPP_SPI0 */
+	INTEL_GPP(GPP_H00, GPP_VGPIO3_USB0, GPP_VGPIO3_THC3),		/* GPP_VGPIO3 */
 };
 
 static const struct vw_entries mtl_community3_vw[] = {
-	{GPP_H0, GPP_H23},
-	{GPP_F0, GPP_F23},
+	{GPP_H00, GPP_H23},
+	{GPP_F00, GPP_F23},
 };
 
 static const struct pad_group mtl_community4_groups[] = {
-	INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 192),			/* GPP_S */
-	INTEL_GPP(GPP_S0, GPP_JTAG_MBPB0, GPP_JTAG_TRST_B),		/* GPP_JTAG */
+	INTEL_GPP_BASE(GPP_S00, GPP_S00, GPP_S07, 192),			/* GPP_S */
+	INTEL_GPP(GPP_S00, GPP_JTAG_MBPB0, GPP_JTAG_TRST_B),		/* GPP_JTAG */
 };
 
 static const struct pad_group mtl_community5_groups[] = {
-	INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_ACI3C0_CLK_LPBK, 224),	/* GPP_B */
-	INTEL_GPP_BASE(GPP_B0, GPP_D0, GPP_BOOTHALT_B, 256),		/* GPP_D */
-	INTEL_GPP(GPP_B0, GPP_VGPIO0, GPP_VGPIO47),			/* GPP_VGPIO */
+	INTEL_GPP_BASE(GPP_B00, GPP_B00, GPP_ACI3C0_CLK_LPBK, 224),	/* GPP_B */
+	INTEL_GPP_BASE(GPP_B00, GPP_D00, GPP_BOOTHALT_B, 256),		/* GPP_D */
+	INTEL_GPP(GPP_B00, GPP_VGPIO00, GPP_VGPIO47),			/* GPP_VGPIO */
 };
 
 static const struct vw_entries mtl_community5_vw[] = {
-	{GPP_B0, GPP_B23},
-	{GPP_D0, GPP_D23},
+	{GPP_B00, GPP_B23},
+	{GPP_D00, GPP_D23},
 };
 
 static const struct pad_community mtl_communities[] = {
diff --git a/src/soc/intel/meteorlake/include/soc/gpio_defs.h b/src/soc/intel/meteorlake/include/soc/gpio_defs.h
index 3594c56dfe..8b5d2d94fa 100644
--- a/src/soc/intel/meteorlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/meteorlake/include/soc/gpio_defs.h
@@ -33,16 +33,16 @@
  */
 
 /* Group V */
-#define GPP_V0_IRQ				0x18
-#define GPP_V1_IRQ				0x19
-#define GPP_V2_IRQ				0x1A
-#define GPP_V3_IRQ				0x1B
-#define GPP_V4_IRQ				0x1C
-#define GPP_V5_IRQ				0x1D
-#define GPP_V6_IRQ				0x1E
-#define GPP_V7_IRQ				0x1F
-#define GPP_V8_IRQ				0x20
-#define GPP_V9_IRQ				0x21
+#define GPP_V00_IRQ				0x18
+#define GPP_V01_IRQ				0x19
+#define GPP_V02_IRQ				0x1A
+#define GPP_V03_IRQ				0x1B
+#define GPP_V04_IRQ				0x1C
+#define GPP_V05_IRQ				0x1D
+#define GPP_V06_IRQ				0x1E
+#define GPP_V07_IRQ				0x1F
+#define GPP_V08_IRQ				0x20
+#define GPP_V09_IRQ				0x21
 #define GPP_V10_IRQ				0x22
 #define GPP_V11_IRQ				0x23
 #define GPP_V12_IRQ				0x24
@@ -59,16 +59,16 @@
 #define GPP_V23_IRQ				0x2F
 
 /* Group C */
-#define GPP_C0_IRQ				0x30
-#define GPP_C1_IRQ				0x31
-#define GPP_C2_IRQ				0x32
-#define GPP_C3_IRQ				0x33
-#define GPP_C4_IRQ				0x34
-#define GPP_C5_IRQ				0x35
-#define GPP_C6_IRQ				0x36
-#define GPP_C7_IRQ				0x37
-#define GPP_C8_IRQ				0x38
-#define GPP_C9_IRQ				0x39
+#define GPP_C00_IRQ				0x30
+#define GPP_C01_IRQ				0x31
+#define GPP_C02_IRQ				0x32
+#define GPP_C03_IRQ				0x33
+#define GPP_C04_IRQ				0x34
+#define GPP_C05_IRQ				0x35
+#define GPP_C06_IRQ				0x36
+#define GPP_C07_IRQ				0x37
+#define GPP_C08_IRQ				0x38
+#define GPP_C09_IRQ				0x39
 #define GPP_C10_IRQ				0x3A
 #define GPP_C11_IRQ				0x3B
 #define GPP_C12_IRQ				0x3C
@@ -85,16 +85,16 @@
 #define GPP_C23_IRQ				0x47
 
 /* Group A */
-#define GPP_A0_IRQ				0x48
-#define GPP_A1_IRQ				0x49
-#define GPP_A2_IRQ				0x4A
-#define GPP_A3_IRQ				0x4B
-#define GPP_A4_IRQ				0x4C
-#define GPP_A5_IRQ				0x4D
-#define GPP_A6_IRQ				0x4E
-#define GPP_A7_IRQ				0x4F
-#define GPP_A8_IRQ				0x50
-#define GPP_A9_IRQ				0x51
+#define GPP_A00_IRQ				0x48
+#define GPP_A01_IRQ				0x49
+#define GPP_A02_IRQ				0x4A
+#define GPP_A03_IRQ				0x4B
+#define GPP_A04_IRQ				0x4C
+#define GPP_A05_IRQ				0x4D
+#define GPP_A06_IRQ				0x4E
+#define GPP_A07_IRQ				0x4F
+#define GPP_A08_IRQ				0x50
+#define GPP_A09_IRQ				0x51
 #define GPP_A10_IRQ				0x52
 #define GPP_A11_IRQ				0x53
 #define GPP_A12_IRQ				0x54
@@ -111,16 +111,16 @@
 #define GPP_A23_IRQ				0x5F
 
 /* Group E */
-#define GPP_E0_IRQ				0x60
-#define GPP_E1_IRQ				0x61
-#define GPP_E2_IRQ				0x62
-#define GPP_E3_IRQ				0x63
-#define GPP_E4_IRQ				0x64
-#define GPP_E5_IRQ				0x65
-#define GPP_E6_IRQ				0x66
-#define GPP_E7_IRQ				0x67
-#define GPP_E8_IRQ				0x68
-#define GPP_E9_IRQ				0x69
+#define GPP_E00_IRQ				0x60
+#define GPP_E01_IRQ				0x61
+#define GPP_E02_IRQ				0x62
+#define GPP_E03_IRQ				0x63
+#define GPP_E04_IRQ				0x64
+#define GPP_E05_IRQ				0x65
+#define GPP_E06_IRQ				0x66
+#define GPP_E07_IRQ				0x67
+#define GPP_E08_IRQ				0x68
+#define GPP_E09_IRQ				0x69
 #define GPP_E10_IRQ				0x6A
 #define GPP_E11_IRQ				0x6B
 #define GPP_E12_IRQ				0x6C
@@ -137,16 +137,16 @@
 #define GPP_E23_IRQ				0x77
 
 /* Group H */
-#define GPP_H0_IRQ				0x18
-#define GPP_H1_IRQ				0x19
-#define GPP_H2_IRQ				0x1A
-#define GPP_H3_IRQ				0x1B
-#define GPP_H4_IRQ				0x1C
-#define GPP_H5_IRQ				0x1D
-#define GPP_H6_IRQ				0x1E
-#define GPP_H7_IRQ				0x1F
-#define GPP_H8_IRQ				0x20
-#define GPP_H9_IRQ				0x21
+#define GPP_H00_IRQ				0x18
+#define GPP_H01_IRQ				0x19
+#define GPP_H02_IRQ				0x1A
+#define GPP_H03_IRQ				0x1B
+#define GPP_H04_IRQ				0x1C
+#define GPP_H05_IRQ				0x1D
+#define GPP_H06_IRQ				0x1E
+#define GPP_H07_IRQ				0x1F
+#define GPP_H08_IRQ				0x20
+#define GPP_H09_IRQ				0x21
 #define GPP_H10_IRQ				0x22
 #define GPP_H11_IRQ				0x23
 #define GPP_H12_IRQ				0x24
@@ -163,16 +163,16 @@
 #define GPP_H23_IRQ				0x2F
 
 /* Group F */
-#define GPP_F0_IRQ				0x30
-#define GPP_F1_IRQ				0x31
-#define GPP_F2_IRQ				0x32
-#define GPP_F3_IRQ				0x33
-#define GPP_F4_IRQ				0x34
-#define GPP_F5_IRQ				0x35
-#define GPP_F6_IRQ				0x36
-#define GPP_F7_IRQ				0x37
-#define GPP_F8_IRQ				0x38
-#define GPP_F9_IRQ				0x39
+#define GPP_F00_IRQ				0x30
+#define GPP_F01_IRQ				0x31
+#define GPP_F02_IRQ				0x32
+#define GPP_F03_IRQ				0x33
+#define GPP_F04_IRQ				0x34
+#define GPP_F05_IRQ				0x35
+#define GPP_F06_IRQ				0x36
+#define GPP_F07_IRQ				0x37
+#define GPP_F08_IRQ				0x38
+#define GPP_F09_IRQ				0x39
 #define GPP_F10_IRQ				0x3A
 #define GPP_F11_IRQ				0x3B
 #define GPP_F12_IRQ				0x3C
@@ -189,26 +189,26 @@
 #define GPP_F23_IRQ				0x47
 
 /* Group S */
-#define GPP_S0_IRQ				0x50
-#define GPP_S1_IRQ				0x51
-#define GPP_S2_IRQ				0x52
-#define GPP_S3_IRQ				0x53
-#define GPP_S4_IRQ				0x54
-#define GPP_S5_IRQ				0x55
-#define GPP_S6_IRQ				0x56
-#define GPP_S7_IRQ				0x57
+#define GPP_S00_IRQ				0x50
+#define GPP_S01_IRQ				0x51
+#define GPP_S02_IRQ				0x52
+#define GPP_S03_IRQ				0x53
+#define GPP_S04_IRQ				0x54
+#define GPP_S05_IRQ				0x55
+#define GPP_S06_IRQ				0x56
+#define GPP_S07_IRQ				0x57
 
 /* Group B */
-#define GPP_B0_IRQ				0x58
-#define GPP_B1_IRQ				0x59
-#define GPP_B2_IRQ				0x5A
-#define GPP_B3_IRQ				0x5B
-#define GPP_B4_IRQ				0x5C
-#define GPP_B5_IRQ				0x5D
-#define GPP_B6_IRQ				0x5E
-#define GPP_B7_IRQ				0x5F
-#define GPP_B8_IRQ				0x60
-#define GPP_B9_IRQ				0x61
+#define GPP_B00_IRQ				0x58
+#define GPP_B01_IRQ				0x59
+#define GPP_B02_IRQ				0x5A
+#define GPP_B03_IRQ				0x5B
+#define GPP_B04_IRQ				0x5C
+#define GPP_B05_IRQ				0x5D
+#define GPP_B06_IRQ				0x5E
+#define GPP_B07_IRQ				0x5F
+#define GPP_B08_IRQ				0x60
+#define GPP_B09_IRQ				0x61
 #define GPP_B10_IRQ				0x62
 #define GPP_B11_IRQ				0x63
 #define GPP_B12_IRQ				0x64
@@ -225,16 +225,16 @@
 #define GPP_B23_IRQ				0x6F
 
 /* Group D */
-#define GPP_D0_IRQ				0x70
-#define GPP_D1_IRQ				0x71
-#define GPP_D2_IRQ				0x72
-#define GPP_D3_IRQ				0x73
-#define GPP_D4_IRQ				0x74
-#define GPP_D5_IRQ				0x75
-#define GPP_D6_IRQ				0x76
-#define GPP_D7_IRQ				0x77
-#define GPP_D8_IRQ				0x18
-#define GPP_D9_IRQ				0x19
+#define GPP_D00_IRQ				0x70
+#define GPP_D01_IRQ				0x71
+#define GPP_D02_IRQ				0x72
+#define GPP_D03_IRQ				0x73
+#define GPP_D04_IRQ				0x74
+#define GPP_D05_IRQ				0x75
+#define GPP_D06_IRQ				0x76
+#define GPP_D07_IRQ				0x77
+#define GPP_D08_IRQ				0x18
+#define GPP_D09_IRQ				0x19
 #define GPP_D10_IRQ				0x1A
 #define GPP_D11_IRQ				0x1B
 #define GPP_D12_IRQ				0x1C
diff --git a/src/soc/intel/meteorlake/include/soc/gpio_soc_defs.h b/src/soc/intel/meteorlake/include/soc/gpio_soc_defs.h
index 9f7cd9643c..09f9b2b3b6 100644
--- a/src/soc/intel/meteorlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/meteorlake/include/soc/gpio_soc_defs.h
@@ -60,17 +60,17 @@
  * | Pad End Number   |    28   |
  * +------------------+---------+
  */
-#define GPP_V0			INC(GPP_VIDALERT_B)
-#define GPP_V1			INC(GPP_V0)
-#define GPP_V2			INC(GPP_V1)
-#define GPP_V3			INC(GPP_V2)
-#define GPP_V4			INC(GPP_V3)
-#define GPP_V5			INC(GPP_V4)
-#define GPP_V6			INC(GPP_V5)
-#define GPP_V7			INC(GPP_V6)
-#define GPP_V8			INC(GPP_V7)
-#define GPP_V9			INC(GPP_V8)
-#define GPP_V10			INC(GPP_V9)
+#define GPP_V00			INC(GPP_VIDALERT_B)
+#define GPP_V01			INC(GPP_V00)
+#define GPP_V02			INC(GPP_V01)
+#define GPP_V03			INC(GPP_V02)
+#define GPP_V04			INC(GPP_V03)
+#define GPP_V05			INC(GPP_V04)
+#define GPP_V06			INC(GPP_V05)
+#define GPP_V07			INC(GPP_V06)
+#define GPP_V08			INC(GPP_V07)
+#define GPP_V09			INC(GPP_V08)
+#define GPP_V10			INC(GPP_V09)
 #define GPP_V11			INC(GPP_V10)
 #define GPP_V12			INC(GPP_V11)
 #define GPP_V13			INC(GPP_V12)
@@ -96,17 +96,17 @@
  * | Pad End Number   |    52   |
  * +------------------+---------+
  */
-#define GPP_C0			INC(GPP_V23)
-#define GPP_C1			INC(GPP_C0)
-#define GPP_C2			INC(GPP_C1)
-#define GPP_C3			INC(GPP_C2)
-#define GPP_C4			INC(GPP_C3)
-#define GPP_C5			INC(GPP_C4)
-#define GPP_C6			INC(GPP_C5)
-#define GPP_C7			INC(GPP_C6)
-#define GPP_C8			INC(GPP_C7)
-#define GPP_C9			INC(GPP_C8)
-#define GPP_C10			INC(GPP_C9)
+#define GPP_C00			INC(GPP_V23)
+#define GPP_C01			INC(GPP_C00)
+#define GPP_C02			INC(GPP_C01)
+#define GPP_C03			INC(GPP_C02)
+#define GPP_C04			INC(GPP_C03)
+#define GPP_C05			INC(GPP_C04)
+#define GPP_C06			INC(GPP_C05)
+#define GPP_C07			INC(GPP_C06)
+#define GPP_C08			INC(GPP_C07)
+#define GPP_C09			INC(GPP_C08)
+#define GPP_C10			INC(GPP_C09)
 #define GPP_C11			INC(GPP_C10)
 #define GPP_C12			INC(GPP_C11)
 #define GPP_C13			INC(GPP_C12)
@@ -136,17 +136,17 @@
  * | Pad End Number   |    77   |
  * +------------------+---------+
  */
-#define GPP_A0			INC(GPP_C23)
-#define GPP_A1			INC(GPP_A0)
-#define GPP_A2			INC(GPP_A1)
-#define GPP_A3			INC(GPP_A2)
-#define GPP_A4			INC(GPP_A3)
-#define GPP_A5			INC(GPP_A4)
-#define GPP_A6			INC(GPP_A5)
-#define GPP_A7			INC(GPP_A6)
-#define GPP_A8			INC(GPP_A7)
-#define GPP_A9			INC(GPP_A8)
-#define GPP_A10			INC(GPP_A9)
+#define GPP_A00			INC(GPP_C23)
+#define GPP_A01			INC(GPP_A00)
+#define GPP_A02			INC(GPP_A01)
+#define GPP_A03			INC(GPP_A02)
+#define GPP_A04			INC(GPP_A03)
+#define GPP_A05			INC(GPP_A04)
+#define GPP_A06			INC(GPP_A05)
+#define GPP_A07			INC(GPP_A06)
+#define GPP_A08			INC(GPP_A07)
+#define GPP_A09			INC(GPP_A08)
+#define GPP_A10			INC(GPP_A09)
 #define GPP_A11			INC(GPP_A10)
 #define GPP_A12			INC(GPP_A11)
 #define GPP_A13			INC(GPP_A12)
@@ -173,17 +173,17 @@
  * | Pad End Number   |    102  |
  * +------------------+---------+
  */
-#define GPP_E0			INC(GPP_ESPI_CLK_LPBK)
-#define GPP_E1			INC(GPP_E0)
-#define GPP_E2			INC(GPP_E1)
-#define GPP_E3			INC(GPP_E2)
-#define GPP_E4			INC(GPP_E3)
-#define GPP_E5			INC(GPP_E4)
-#define GPP_E6			INC(GPP_E5)
-#define GPP_E7			INC(GPP_E6)
-#define GPP_E8			INC(GPP_E7)
-#define GPP_E9			INC(GPP_E8)
-#define GPP_E10			INC(GPP_E9)
+#define GPP_E00			INC(GPP_ESPI_CLK_LPBK)
+#define GPP_E01			INC(GPP_E00)
+#define GPP_E02			INC(GPP_E01)
+#define GPP_E03			INC(GPP_E02)
+#define GPP_E04			INC(GPP_E03)
+#define GPP_E05			INC(GPP_E04)
+#define GPP_E06			INC(GPP_E05)
+#define GPP_E07			INC(GPP_E06)
+#define GPP_E08			INC(GPP_E07)
+#define GPP_E09			INC(GPP_E08)
+#define GPP_E10			INC(GPP_E09)
 #define GPP_E11			INC(GPP_E10)
 #define GPP_E12			INC(GPP_E11)
 #define GPP_E13			INC(GPP_E12)
@@ -199,9 +199,9 @@
 #define GPP_E23			INC(GPP_E22)
 #define GPP_THC0_GSPI_CLK_LPBK	INC(GPP_E23)
 
-#define GPIO_COM1_START		GPP_A0
+#define GPIO_COM1_START		GPP_A00
 #define GPIO_COM1_END		GPP_THC0_GSPI_CLK_LPBK
-#define NUM_GPIO_COM1_PADS	(GPP_THC0_GSPI_CLK_LPBK - GPP_A0 + 1)
+#define NUM_GPIO_COM1_PADS	(GPP_THC0_GSPI_CLK_LPBK - GPP_A00 + 1)
 
 /*
  * +----------------------------+
@@ -214,17 +214,17 @@
  * | Pad End Number   |    128  |
  * +------------------+---------+
  */
-#define GPP_H0			INC(GPP_THC0_GSPI_CLK_LPBK)
-#define GPP_H1			INC(GPP_H0)
-#define GPP_H2			INC(GPP_H1)
-#define GPP_H3			INC(GPP_H2)
-#define GPP_H4			INC(GPP_H3)
-#define GPP_H5			INC(GPP_H4)
-#define GPP_H6			INC(GPP_H5)
-#define GPP_H7			INC(GPP_H6)
-#define GPP_H8			INC(GPP_H7)
-#define GPP_H9			INC(GPP_H8)
-#define GPP_H10			INC(GPP_H9)
+#define GPP_H00			INC(GPP_THC0_GSPI_CLK_LPBK)
+#define GPP_H01			INC(GPP_H00)
+#define GPP_H02			INC(GPP_H01)
+#define GPP_H03			INC(GPP_H02)
+#define GPP_H04			INC(GPP_H03)
+#define GPP_H05			INC(GPP_H04)
+#define GPP_H06			INC(GPP_H05)
+#define GPP_H07			INC(GPP_H06)
+#define GPP_H08			INC(GPP_H07)
+#define GPP_H09			INC(GPP_H08)
+#define GPP_H10			INC(GPP_H09)
 #define GPP_H11			INC(GPP_H10)
 #define GPP_H12			INC(GPP_H11)
 #define GPP_H13			INC(GPP_H12)
@@ -252,17 +252,17 @@
  * | Pad End Number   |    154  |
  * +------------------+---------+
  */
-#define GPP_F0			INC(GPP_LPI3C0_CLK_LPBK)
-#define GPP_F1			INC(GPP_F0)
-#define GPP_F2			INC(GPP_F1)
-#define GPP_F3			INC(GPP_F2)
-#define GPP_F4			INC(GPP_F3)
-#define GPP_F5			INC(GPP_F4)
-#define GPP_F6			INC(GPP_F5)
-#define GPP_F7			INC(GPP_F6)
-#define GPP_F8			INC(GPP_F7)
-#define GPP_F9			INC(GPP_F8)
-#define GPP_F10			INC(GPP_F9)
+#define GPP_F00			INC(GPP_LPI3C0_CLK_LPBK)
+#define GPP_F01			INC(GPP_F00)
+#define GPP_F02			INC(GPP_F01)
+#define GPP_F03			INC(GPP_F02)
+#define GPP_F04			INC(GPP_F03)
+#define GPP_F05			INC(GPP_F04)
+#define GPP_F06			INC(GPP_F05)
+#define GPP_F07			INC(GPP_F06)
+#define GPP_F08			INC(GPP_F07)
+#define GPP_F09			INC(GPP_F08)
+#define GPP_F10			INC(GPP_F09)
 #define GPP_F11			INC(GPP_F10)
 #define GPP_F12			INC(GPP_F11)
 #define GPP_F13			INC(GPP_F12)
@@ -332,9 +332,9 @@
 #define GPP_VGPIO3_THC2		INC(GPP_VGPIO3_THC1)
 #define GPP_VGPIO3_THC3		INC(GPP_VGPIO3_THC2)
 
-#define GPIO_COM3_START		GPP_H0
+#define GPIO_COM3_START		GPP_H00
 #define GPIO_COM3_END		GPP_VGPIO3_THC3
-#define NUM_GPIO_COM3_PADS	(GPP_VGPIO3_THC3 - GPP_H0 + 1)
+#define NUM_GPIO_COM3_PADS	(GPP_VGPIO3_THC3 - GPP_H00 + 1)
 
 /*
  * +----------------------------+
@@ -347,14 +347,14 @@
  * | Pad End Number   |    191  |
  * +------------------+---------+
  */
-#define GPP_S0			INC(GPP_VGPIO3_THC3)
-#define GPP_S1			INC(GPP_S0)
-#define GPP_S2			INC(GPP_S1)
-#define GPP_S3			INC(GPP_S2)
-#define GPP_S4			INC(GPP_S3)
-#define GPP_S5			INC(GPP_S4)
-#define GPP_S6			INC(GPP_S5)
-#define GPP_S7			INC(GPP_S6)
+#define GPP_S00			INC(GPP_VGPIO3_THC3)
+#define GPP_S01			INC(GPP_S00)
+#define GPP_S02			INC(GPP_S01)
+#define GPP_S03			INC(GPP_S02)
+#define GPP_S04			INC(GPP_S03)
+#define GPP_S05			INC(GPP_S04)
+#define GPP_S06			INC(GPP_S05)
+#define GPP_S07			INC(GPP_S06)
 
 /*
  * +----------------------------+
@@ -367,7 +367,7 @@
  * | Pad End Number   |    203  |
  * +------------------+---------+
  */
-#define GPP_JTAG_MBPB0		INC(GPP_S7)
+#define GPP_JTAG_MBPB0		INC(GPP_S07)
 #define GPP_JTAG_MBPB1		INC(GPP_JTAG_MBPB0)
 #define GPP_JTAG_MBPB2		INC(GPP_JTAG_MBPB1)
 #define GPP_JTAG_MBPB3		INC(GPP_JTAG_MBPB2)
@@ -380,9 +380,9 @@
 #define GPP_DBG_PMODE		INC(GPP_JTAG_TCK)
 #define GPP_JTAG_TRST_B		INC(GPP_DBG_PMODE)
 
-#define GPIO_COM4_START		GPP_S0
+#define GPIO_COM4_START		GPP_S00
 #define GPIO_COM4_END		GPP_JTAG_TRST_B
-#define NUM_GPIO_COM4_PADS	(GPP_JTAG_TRST_B - GPP_S0 + 1)
+#define NUM_GPIO_COM4_PADS	(GPP_JTAG_TRST_B - GPP_S00 + 1)
 
 /*
  * +----------------------------+
@@ -395,17 +395,17 @@
  * | Pad End Number   |    228  |
  * +------------------+---------+
  */
-#define GPP_B0			INC(GPP_JTAG_TRST_B)
-#define GPP_B1			INC(GPP_B0)
-#define GPP_B2			INC(GPP_B1)
-#define GPP_B3			INC(GPP_B2)
-#define GPP_B4			INC(GPP_B3)
-#define GPP_B5			INC(GPP_B4)
-#define GPP_B6			INC(GPP_B5)
-#define GPP_B7			INC(GPP_B6)
-#define GPP_B8			INC(GPP_B7)
-#define GPP_B9			INC(GPP_B8)
-#define GPP_B10			INC(GPP_B9)
+#define GPP_B00			INC(GPP_JTAG_TRST_B)
+#define GPP_B01			INC(GPP_B00)
+#define GPP_B02			INC(GPP_B01)
+#define GPP_B03			INC(GPP_B02)
+#define GPP_B04			INC(GPP_B03)
+#define GPP_B05			INC(GPP_B04)
+#define GPP_B06			INC(GPP_B05)
+#define GPP_B07			INC(GPP_B06)
+#define GPP_B08			INC(GPP_B07)
+#define GPP_B09			INC(GPP_B08)
+#define GPP_B10			INC(GPP_B09)
 #define GPP_B11			INC(GPP_B10)
 #define GPP_B12			INC(GPP_B11)
 #define GPP_B13			INC(GPP_B12)
@@ -432,17 +432,17 @@
  * | Pad End Number   |    253  |
  * +------------------+---------+
  */
-#define GPP_D0			INC(GPP_ACI3C0_CLK_LPBK)
-#define GPP_D1			INC(GPP_D0)
-#define GPP_D2			INC(GPP_D1)
-#define GPP_D3			INC(GPP_D2)
-#define GPP_D4			INC(GPP_D3)
-#define GPP_D5			INC(GPP_D4)
-#define GPP_D6			INC(GPP_D5)
-#define GPP_D7			INC(GPP_D6)
-#define GPP_D8			INC(GPP_D7)
-#define GPP_D9			INC(GPP_D8)
-#define GPP_D10			INC(GPP_D9)
+#define GPP_D00			INC(GPP_ACI3C0_CLK_LPBK)
+#define GPP_D01			INC(GPP_D00)
+#define GPP_D02			INC(GPP_D01)
+#define GPP_D03			INC(GPP_D02)
+#define GPP_D04			INC(GPP_D03)
+#define GPP_D05			INC(GPP_D04)
+#define GPP_D06			INC(GPP_D05)
+#define GPP_D07			INC(GPP_D06)
+#define GPP_D08			INC(GPP_D07)
+#define GPP_D09			INC(GPP_D08)
+#define GPP_D10			INC(GPP_D09)
 #define GPP_D11			INC(GPP_D10)
 #define GPP_D12			INC(GPP_D11)
 #define GPP_D13			INC(GPP_D12)
@@ -469,14 +469,14 @@
  * | Pad End Number   |    288  |
  * +------------------+---------+
  */
-#define GPP_VGPIO0		INC(GPP_BOOTHALT_B)
-#define GPP_VGPIO4		INC(GPP_VGPIO0)
-#define GPP_VGPIO5		INC(GPP_VGPIO4)
-#define GPP_VGPIO6		INC(GPP_VGPIO5)
-#define GPP_VGPIO7		INC(GPP_VGPIO6)
-#define GPP_VGPIO8		INC(GPP_VGPIO7)
-#define GPP_VGPIO9		INC(GPP_VGPIO8)
-#define GPP_VGPIO10		INC(GPP_VGPIO9)
+#define GPP_VGPIO00		INC(GPP_BOOTHALT_B)
+#define GPP_VGPIO04		INC(GPP_VGPIO00)
+#define GPP_VGPIO05		INC(GPP_VGPIO04)
+#define GPP_VGPIO06		INC(GPP_VGPIO05)
+#define GPP_VGPIO07		INC(GPP_VGPIO06)
+#define GPP_VGPIO08		INC(GPP_VGPIO07)
+#define GPP_VGPIO09		INC(GPP_VGPIO08)
+#define GPP_VGPIO10		INC(GPP_VGPIO09)
 #define GPP_VGPIO11		INC(GPP_VGPIO10)
 #define GPP_VGPIO12		INC(GPP_VGPIO11)
 #define GPP_VGPIO13		INC(GPP_VGPIO12)
@@ -505,9 +505,9 @@
 #define GPP_VGPIO46		INC(GPP_VGPIO45)
 #define GPP_VGPIO47		INC(GPP_VGPIO46)
 
-#define GPIO_COM5_START		GPP_B0
+#define GPIO_COM5_START		GPP_B00
 #define GPIO_COM5_END		GPP_VGPIO47
-#define NUM_GPIO_COM5_PADS	(GPP_VGPIO47 - GPP_B0 + 1)
+#define NUM_GPIO_COM5_PADS	(GPP_VGPIO47 - GPP_B00 + 1)
 
 #define TOTAL_GPIO_COMM		(COMM_5 + 1)
 #define TOTAL_PADS		(GPIO_COM5_END + 1)