diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2009-05-27 18:55:19 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2009-05-27 18:55:19 +0000 |
| commit | 7365004424f58db813a092c24c404ec99507765f (patch) | |
| tree | a295b73549800b36b6e53458b5c8ee7cf6ff2a97 | |
| parent | 5c044c732fc28b09eb58956a85b141af194f2b94 (diff) | |
First batch of indent-aided code cleanups, more will follow.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
27 files changed, 720 insertions, 779 deletions
diff --git a/src/northbridge/via/vx800/chip.h b/src/northbridge/via/vx800/chip.h index 700a398d5c..7d7153ceda 100644 --- a/src/northbridge/via/vx800/chip.h +++ b/src/northbridge/via/vx800/chip.h @@ -17,8 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -struct northbridge_via_vx800_config -{ +struct northbridge_via_vx800_config { }; extern struct chip_operations northbridge_via_vx800_ops; diff --git a/src/northbridge/via/vx800/clk_ctrl.c b/src/northbridge/via/vx800/clk_ctrl.c index 13edc1f996..ec070ee1c7 100644 --- a/src/northbridge/via/vx800/clk_ctrl.c +++ b/src/northbridge/via/vx800/clk_ctrl.c @@ -17,11 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -void DutyCycleCtrl(DRAM_SYS_ATTR * DramAttr) +void DutyCycleCtrl(DRAM_SYS_ATTR *DramAttr) { - u8 Data; - u8 FreqId; - u8 i; + u8 Data, FreqId, i; if (DIMMFREQ_800 == DramAttr->DramFreq) FreqId = 2; @@ -34,64 +32,54 @@ void DutyCycleCtrl(DRAM_SYS_ATTR * DramAttr) else FreqId = 5; - if (DramAttr->RankNumChA > 0) { // 1 rank + if (DramAttr->RankNumChA > 0) { /* 1 rank */ for (i = 0; i < DUTY_CYCLE_REG_NUM; i++) { - Data = - pci_read_config8(MEMCTRL, - ChA_Duty_Control_DDR2[i][0]); - Data &= ChA_Duty_Control_DDR2[i][1]; /*Mask */ - Data |= ChA_Duty_Control_DDR2[i][FreqId]; /*set Value */ + Data = pci_read_config8(MEMCTRL, + ChA_Duty_Control_DDR2[i][0]); + Data &= ChA_Duty_Control_DDR2[i][1]; /* mask */ + Data |= ChA_Duty_Control_DDR2[i][FreqId]; /* set val */ pci_write_config8(MEMCTRL, - ChA_Duty_Control_DDR2[i][0], - Data); + ChA_Duty_Control_DDR2[i][0], Data); } } - if (1 == ENABLE_CHC) { // 1 rank + + if (1 == ENABLE_CHC) { /* 1 rank */ for (i = 0; i < DUTY_CYCLE_REG_NUM; i++) { - Data = - pci_read_config8(MEMCTRL, - ChB_Duty_Control_DDR2[i][0]); - Data &= ChB_Duty_Control_DDR2[i][1]; /*Mask */ - Data |= ChB_Duty_Control_DDR2[i][FreqId]; /*set Value */ + Data = pci_read_config8(MEMCTRL, + ChB_Duty_Control_DDR2[i][0]); + Data &= ChB_Duty_Control_DDR2[i][1]; /* mask */ + Data |= ChB_Duty_Control_DDR2[i][FreqId]; /* set val */ pci_write_config8(MEMCTRL, - ChB_Duty_Control_DDR2[i][0], - Data); + ChB_Duty_Control_DDR2[i][0], Data); } } - } /* -DRAM clock phase and delay control -*/ -//sub routine list -void ClkPhsCtrlFBMDDR2(DRAM_SYS_ATTR * DramAttr); - -void WrtDataPhsCtrl(DRAM_SYS_ATTR * DramAttr); - -void DQDQSOutputDlyCtrl(DRAM_SYS_ATTR * DramAttr); - -void DQSInputCaptureCtrl(DRAM_SYS_ATTR * DramAttr); - -void DCLKPhsCtrl(DRAM_SYS_ATTR * DramAttr); + * DRAM clock phase and delay control + */ +/* Subroutine list */ +void ClkPhsCtrlFBMDDR2(DRAM_SYS_ATTR *DramAttr); +void WrtDataPhsCtrl(DRAM_SYS_ATTR *DramAttr); +void DQDQSOutputDlyCtrl(DRAM_SYS_ATTR *DramAttr); +void DQSInputCaptureCtrl(DRAM_SYS_ATTR *DramAttr); +void DCLKPhsCtrl(DRAM_SYS_ATTR *DramAttr); -void DRAMClkCtrl(DRAM_SYS_ATTR * DramAttr) +void DRAMClkCtrl(DRAM_SYS_ATTR *DramAttr) { - /*write data clock phase control */ + /* Write data clock phase control. */ WrtDataPhsCtrl(DramAttr); - /*clock phase control */ + /* Clock phase control */ ClkPhsCtrlFBMDDR2(DramAttr); /**/ DQDQSOutputDlyCtrl(DramAttr); /**/ DQSInputCaptureCtrl(DramAttr); DCLKPhsCtrl(DramAttr); } -void ClkPhsCtrlFBMDDR2(DRAM_SYS_ATTR * DramAttr) +void ClkPhsCtrlFBMDDR2(DRAM_SYS_ATTR *DramAttr) { - u8 Data; - - u8 FreqId, i; + u8 Data, FreqId, i; if (DramAttr->DramFreq == DIMMFREQ_800) FreqId = 2; @@ -103,54 +91,45 @@ void ClkPhsCtrlFBMDDR2(DRAM_SYS_ATTR * DramAttr) FreqId = 5; else FreqId = 5; - /*channel A */// 2~4 Rank - if (DramAttr->RankNumChA == 1) { // 1 rank + + /* Channel A */ + // 2~4 Rank + if (DramAttr->RankNumChA == 1) { /* 1 rank */ for (i = 0; i < 3; i++) { - Data = - pci_read_config8(MEMCTRL, - DDR2_ChA_Clk_Phase_Table_1R[i] - [0]); - Data &= DDR2_ChA_Clk_Phase_Table_1R[i][1]; /*Mask */ - Data |= DDR2_ChA_Clk_Phase_Table_1R[i][FreqId]; /*set Value */ + Data = pci_read_config8(MEMCTRL, + DDR2_ChA_Clk_Phase_Table_1R[i][0]); + Data &= DDR2_ChA_Clk_Phase_Table_1R[i][1]; /* mask */ + Data |= DDR2_ChA_Clk_Phase_Table_1R[i][FreqId]; /* set val */ pci_write_config8(MEMCTRL, - DDR2_ChA_Clk_Phase_Table_1R[i] - [0], Data); + DDR2_ChA_Clk_Phase_Table_1R[i][0], Data); } - } else if (DramAttr->RankNumChA > 1) { // 2~4 Rank + } else if (DramAttr->RankNumChA > 1) { /* 2~4 Rank */ for (i = 0; i < 3; i++) { - Data = - pci_read_config8(MEMCTRL, - DDR2_ChA_Clk_Phase_Table_2R[i] - [0]); - Data &= DDR2_ChA_Clk_Phase_Table_2R[i][1]; /*Mask */ - Data |= DDR2_ChA_Clk_Phase_Table_2R[i][FreqId]; /*set Value */ + Data = pci_read_config8(MEMCTRL, + DDR2_ChA_Clk_Phase_Table_2R[i][0]); + Data &= DDR2_ChA_Clk_Phase_Table_2R[i][1]; /* mask */ + Data |= DDR2_ChA_Clk_Phase_Table_2R[i][FreqId]; /* set val */ pci_write_config8(MEMCTRL, - DDR2_ChA_Clk_Phase_Table_2R[i] - [0], Data); + DDR2_ChA_Clk_Phase_Table_2R[i][0], Data); } } #if ENABLE_CHB - if (DramAttr->RankNumChB > 0) { // 1 rank + if (DramAttr->RankNumChB > 0) { /* 1 rank */ for (i = 0; i < 3; i++) { - Data = - pci_read_config8(MEMCTRL, - DDR2_ChB_Clk_Phase_Table_1R[i] - [0]); - Data &= DDR2_ChB_Clk_Phase_Table_1R[i][1]; /*Mask */ - Data |= DDR2_ChB_Clk_Phase_Table_1R[i][FreqId]; /*set Value */ + Data = pci_read_config8(MEMCTRL, + DDR2_ChB_Clk_Phase_Table_1R[i][0]); + Data &= DDR2_ChB_Clk_Phase_Table_1R[i][1]; /* mask */ + Data |= DDR2_ChB_Clk_Phase_Table_1R[i][FreqId]; /* set val */ pci_write_config8(MEMCTRL, - DDR2_ChB_Clk_Phase_Table_1R[i] - [0], Data); + DDR2_ChB_Clk_Phase_Table_1R[i][0], Data); } } #endif } -void WrtDataPhsCtrl(DRAM_SYS_ATTR * DramAttr) +void WrtDataPhsCtrl(DRAM_SYS_ATTR *DramAttr) { - u8 Data; - u8 FreqId, i; - + u8 Data, FreqId, i; if (DIMMFREQ_800 == DramAttr->DramFreq) FreqId = 2; @@ -163,31 +142,25 @@ void WrtDataPhsCtrl(DRAM_SYS_ATTR * DramAttr) else FreqId = 5; - if (DramAttr->RankNumChA > 0) { // 1 rank + if (DramAttr->RankNumChA > 0) { /* 1 rank */ for (i = 0; i < WrtData_REG_NUM; i++) { - Data = - pci_read_config8(MEMCTRL, - DDR2_ChA_WrtData_Phase_Table - [i][0]); - Data &= DDR2_ChA_WrtData_Phase_Table[i][1]; /*Mask */ - Data |= DDR2_ChA_WrtData_Phase_Table[i][FreqId]; /*set Value */ + Data = pci_read_config8(MEMCTRL, + DDR2_ChA_WrtData_Phase_Table[i][0]); + Data &= DDR2_ChA_WrtData_Phase_Table[i][1]; /* mask */ + Data |= DDR2_ChA_WrtData_Phase_Table[i][FreqId]; /* set val */ pci_write_config8(MEMCTRL, - DDR2_ChA_WrtData_Phase_Table[i] - [0], Data); + DDR2_ChA_WrtData_Phase_Table[i][0], Data); } } #if ENABLE_CHB - if (DramAttr->RankNumChB > 0) { // 1 rank + if (DramAttr->RankNumChB > 0) { /* 1 rank */ for (i = 0; i < WrtData_REG_NUM; i++) { - Data = - pci_read_config8(MEMCTRL, - DDR2_ChB_WrtData_Phase_Table - [i][0]); - Data &= DDR2_ChB_WrtData_Phase_Table[i][1]; /*Mask */ - Data |= DDR2_ChB_WrtData_Phase_Table[i][FreqId]; /*set Value */ + Data = pci_read_config8(MEMCTRL, + DDR2_ChB_WrtData_Phase_Table[i][0]); + Data &= DDR2_ChB_WrtData_Phase_Table[i][1]; /* mask */ + Data |= DDR2_ChB_WrtData_Phase_Table[i][FreqId]; /* set val */ pci_write_config8(MEMCTRL, - DDR2_ChB_WrtData_Phase_Table[i] - [0], Data); + DDR2_ChB_WrtData_Phase_Table[i][0], Data); } } #endif @@ -197,10 +170,9 @@ void WrtDataPhsCtrl(DRAM_SYS_ATTR * DramAttr) pci_write_config8(MEMCTRL, 0x8C, Data); } -void DQDQSOutputDlyCtrl(DRAM_SYS_ATTR * DramAttr) +void DQDQSOutputDlyCtrl(DRAM_SYS_ATTR *DramAttr) { - u8 Data; - u8 FreqId; + u8 Data, FreqId; if (DIMMFREQ_400 == DramAttr->DramFreq) FreqId = 0; @@ -212,6 +184,7 @@ void DQDQSOutputDlyCtrl(DRAM_SYS_ATTR * DramAttr) FreqId = 2; else FreqId = 0; + if (DramAttr->RankNumChA > 0) { Data = DDR2_CHA_DQ_DQS_Delay_Table[FreqId][0]; pci_write_config8(MEMCTRL, 0xf0, Data); @@ -242,10 +215,9 @@ void DQDQSOutputDlyCtrl(DRAM_SYS_ATTR * DramAttr) #endif } -void DQSInputCaptureCtrl(DRAM_SYS_ATTR * DramAttr) +void DQSInputCaptureCtrl(DRAM_SYS_ATTR *DramAttr) { - u8 Data; - u8 FreqId, i; + u8 Data, FreqId, i; if (DIMMFREQ_800 == DramAttr->DramFreq) FreqId = 2; @@ -261,52 +233,49 @@ void DQSInputCaptureCtrl(DRAM_SYS_ATTR * DramAttr) Data = 0x8A; pci_write_config8(MEMCTRL, 0x77, Data); - if (DramAttr->RankNumChA > 0) { // 1 rank + if (DramAttr->RankNumChA > 0) { /* 1 rank */ for (i = 0; i < DQS_INPUT_CAPTURE_REG_NUM; i++) { - Data = - pci_read_config8(MEMCTRL, - DDR2_ChA_DQS_Input_Capture_Tbl - [i][0]); - Data &= DDR2_ChA_DQS_Input_Capture_Tbl[i][1]; /*Mask */ - Data |= DDR2_ChA_DQS_Input_Capture_Tbl[i][FreqId]; /*set Value */ + Data = pci_read_config8(MEMCTRL, + DDR2_ChA_DQS_Input_Capture_Tbl[i][0]); + Data &= DDR2_ChA_DQS_Input_Capture_Tbl[i][1]; /* mask */ + Data |= DDR2_ChA_DQS_Input_Capture_Tbl[i][FreqId]; /* set val */ pci_write_config8(MEMCTRL, - DDR2_ChA_DQS_Input_Capture_Tbl[i] - [0], Data); + DDR2_ChA_DQS_Input_Capture_Tbl[i][0], Data); } } #if ENABLE_CHB - if (DramAttr->RankNumChB > 0) { // 1 rank + if (DramAttr->RankNumChB > 0) { /* 1 rank */ for (i = 0; i < DQS_INPUT_CAPTURE_REG_NUM; i++) { - Data = - pci_read_config8(MEMCTRL, - DDR2_ChB_DQS_Input_Capture_Tbl - [i][0]); - Data &= DDR2_ChB_DQS_Input_Capture_Tbl[i][1]; /*Mask */ - Data |= DDR2_ChB_DQS_Input_Capture_Tbl[i][FreqId]; /*set Value */ + Data = pci_read_config8(MEMCTRL, + DDR2_ChB_DQS_Input_Capture_Tbl[i][0]); + Data &= DDR2_ChB_DQS_Input_Capture_Tbl[i][1]; /* mask */ + Data |= DDR2_ChB_DQS_Input_Capture_Tbl[i][FreqId]; /* set val */ pci_write_config8(MEMCTRL, - DDR2_ChB_DQS_Input_Capture_Tbl[i] - [0], Data); + DDR2_ChB_DQS_Input_Capture_Tbl[i][0], Data); } } #endif } -//This is very important, if you don't set it correctly, dram will be unreliable -//set DCLK Phase control(Reg99H[6:1]) according the DDRII in the dimm -void DCLKPhsCtrl(DRAM_SYS_ATTR * DramAttr) +/* + * This is very important, if you don't set it correctly, DRAM will be + * unreliable, + * + * Set DCLK Phase control(Reg99H[6:1]) according the DDRII in the DIMM. + */ +void DCLKPhsCtrl(DRAM_SYS_ATTR *DramAttr) { u8 Data; - Data = 0; + Data = 0; /* TODO: Can be dropped? */ Data = pci_read_config8(MEMCTRL, 0x99); Data &= 0xE1; - //DDR in Dimm1, MCLKOA[4,3,0] will output MCLK + /* DDR in Dimm1, MCLKOA[4,3,0] will output MCLK */ if (DramAttr->RankPresentMap & 0x03) Data |= 0x09 << 1; - //DDR in Dimm2, MCLKOA[5,2,1] will output MCLK + /* DDR in Dimm2, MCLKOA[5,2,1] will output MCLK */ if (DramAttr->RankPresentMap & 0x0C) Data |= 0x06 << 1; pci_write_config8(MEMCTRL, 0x99, Data); - } diff --git a/src/northbridge/via/vx800/detection.c b/src/northbridge/via/vx800/detection.c index 63fc56b845..51aa9fa302 100644 --- a/src/northbridge/via/vx800/detection.c +++ b/src/northbridge/via/vx800/detection.c @@ -17,25 +17,20 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SMBUS_ADDR_CH_A_1 0xA0 // Dimmx -#define SMBUS_ADDR_CH_A_2 0xA2 // Dimmx -#define SMBUS_ADDR_CH_B_1 0xA4 // Dimmx -#define SMBUS_ADDR_CH_B_2 0xA6 // Dimmx +#define SMBUS_ADDR_CH_A_1 0xA0 /* Dimmx */ +#define SMBUS_ADDR_CH_A_2 0xA2 /* Dimmx */ +#define SMBUS_ADDR_CH_B_1 0xA4 /* Dimmx */ +#define SMBUS_ADDR_CH_B_2 0xA6 /* Dimmx */ -/*read data*/ -CB_STATUS GetSPDData(u8 Slot, u8 Length, u8 * Buf); +/* read data */ +CB_STATUS GetSPDData(u8 Slot, u8 Length, u8 *Buf); +void DRAMCmdRate(DRAM_SYS_ATTR *DramAttr); +CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR *DramAttr); -void DRAMCmdRate(DRAM_SYS_ATTR * DramAttr); - - - -CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR * DramAttr); - -CB_STATUS GetSPDData(u8 Slot, u8 Length, u8 * Buf) +CB_STATUS GetSPDData(u8 Slot, u8 Length, u8 *Buf) { // CB_STATUS Status = CB_NOT_READY; - u8 Val; - u8 i; + u8 Val, i; if (1 > Length || NULL == Buf) return CB_INVALID_PARAMETER; @@ -47,37 +42,42 @@ CB_STATUS GetSPDData(u8 Slot, u8 Length, u8 * Buf) return CB_SUCCESS; } -CB_STATUS DRAMDetect(DRAM_SYS_ATTR * DramAttr) +CB_STATUS DRAMDetect(DRAM_SYS_ATTR *DramAttr) { CB_STATUS Status = CB_SUCCESS; - PRINT_DEBUG_MEM("Dram Detection \r"); + PRINT_DEBUG_MEM("DRAM detection \r"); - /*Read D0F3Rx6C , detect memory type DDR1 or DDR2 */ - // 353 supports DDR2 only + /* Read D0F3Rx6C, detect memory type DDR1 or DDR2. */ + /* 353 supports DDR2 only */ DramAttr->DramType = RAMTYPE_SDRAMDDR2; - /*get information for SPD */ + /* Get information for SPD. */ Status = GetInfoFromSPD(DramAttr); if (CB_SUCCESS == Status) { - /*64bit or 128Bit */ - // - // if (RAMTYPE_SDRAMDDR == DramAttr->DramType) + /* 64bit or 128Bit */ + + // if (RAMTYPE_SDRAMDDR == DramAttr->DramType) - /*select command rate */ + /* Select command rate. */ DRAMCmdRate(DramAttr); } return Status; } - -// Determine 1T or 2T Command Rate: -// To enable 1T command Rate, the system will satisfy the following 3 conditions: -// 1. Each DRAM channel may have 1 or 2 ranks of DIMM. 3/4 ranks can not support 1T command rate -// It's for loading issue. 1T can supports (a). only one socket with two ranks OR -// (b). two sockets each with 1 rank. -// 2. User wishes to enable 1T command rate mode and turn on by Setup menu -// 3. If 1T command rate can be enabled, just set EBP bit here. -void DRAMCmdRate(DRAM_SYS_ATTR * DramAttr) +/* + * Determine 1T or 2T command rate. + * + * To enable 1T command rate, the system will satisfy the following + * three conditions: + * + * 1. Each DRAM channel may have 1 or 2 ranks of DIMM. 3/4 ranks can not + * support 1T command rate. It's for loading issue. 1T can supports + * (a) only one socket with two ranks, OR + * (b) two sockets each with 1 rank. + * 2. User wishes to enable 1T command rate mode and turn on by setup menu. + * 3. If 1T command rate can be enabled, just set EBP bit here. + */ +void DRAMCmdRate(DRAM_SYS_ATTR *DramAttr) { u8 Data; @@ -89,23 +89,22 @@ void DRAMCmdRate(DRAM_SYS_ATTR * DramAttr) pci_write_config8(MEMCTRL, 0x50, Data); } -/*get SPD data and set RANK presence map*/ /* -Sockets0,1 is Channel A / Sockets2,3 is Channel B -socket0 SPD device address 0x50 / socket1 SPD device address 0x51 -socket2 SPD device address 0x52 / socket3 SPD device address 0x53 -*/ -CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR * DramAttr) + * Get SPD data and set RANK presence map. + * + * Sockets0,1 is Channel A / Sockets2,3 is Channel B. + * + * Socket0 SPD device address 0x50 / socket1 SPD device address 0x51 + * Socket2 SPD device address 0x52 / socket3 SPD device address 0x53 + */ +CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR *DramAttr) { CB_STATUS Status; u8 *pSPDDataBuf; - u8 ModuleDataWidth; - u8 ChipWidth; - u8 RankNum; - u8 LoadNum; - u8 Sockets, i; - BOOLEAN bFind; - bFind = FALSE; + u8 ModuleDataWidth, ChipWidth, RankNum, LoadNum, Sockets, i; + BOOLEAN bFind; /* FIXME: We don't have/want BOOLEAN. */ + + bFind = FALSE; /* FIXME: We don't have/want FALSE. */ Status = CB_DEVICE_ERROR; for (Sockets = 0; Sockets < MAX_SOCKETS; Sockets++) { @@ -116,8 +115,7 @@ CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR * DramAttr) Status = CB_NOT_READY; } else { Status = - GetSPDData(Sockets, SPD_DATA_SIZE, - pSPDDataBuf); + GetSPDData(Sockets, SPD_DATA_SIZE, pSPDDataBuf); PRINT_DEBUG_MEM("SPD : \r"); for (i = 0; i < SPD_DATA_SIZE; i++) { PRINT_DEBUG_MEM(" "); @@ -125,49 +123,58 @@ CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR * DramAttr) } } if (CB_SUCCESS == Status) { - /*if Dram Controller detected type not same as the type got from SPD, There are ERROR */ - if (pSPDDataBuf[SPD_MEMORY_TYPE] != - DramAttr->DramType) { - Status = CB_DEVICE_ERROR; /*Memory int error */ - PRINT_DEBUG_MEM - ("Memory Device ERROR: Dram Controller detected type != type got from SPD \r"); + /* + * If DRAM controller detected type not same as the + * type got from SPD, there are ERROR. + */ + if (pSPDDataBuf[SPD_MEMORY_TYPE] != DramAttr->DramType) { + Status = CB_DEVICE_ERROR; /* memory int error */ + PRINT_DEBUG_MEM("Memory Device ERROR: DRAM " + "controller detected type != " + "type got from SPD\r"); break; } DramAttr->DimmInfo[Sockets].bPresence = TRUE; - /*calculate load number (chips number) */ - ModuleDataWidth = - (u8) (DramAttr->DimmInfo[Sockets]. - SPDDataBuf[SPD_SDRAM_MOD_DATA_WIDTH + - 1]); + + /* Calculate load number (chips number). */ + ModuleDataWidth = (u8) (DramAttr-> + DimmInfo[Sockets].SPDDataBuf + [SPD_SDRAM_MOD_DATA_WIDTH + 1]); ModuleDataWidth = (u8) (ModuleDataWidth << 8); - ModuleDataWidth |= - (u8) (DramAttr->DimmInfo[Sockets]. - SPDDataBuf[SPD_SDRAM_MOD_DATA_WIDTH]); - ChipWidth = - (u8) ((DramAttr->DimmInfo[Sockets]. - SPDDataBuf[SPD_SDRAM_WIDTH]) & 0x7F); + ModuleDataWidth |= (u8) (DramAttr-> + DimmInfo[Sockets].SPDDataBuf + [SPD_SDRAM_MOD_DATA_WIDTH]); + ChipWidth = (u8) ((DramAttr-> + DimmInfo[Sockets].SPDDataBuf + [SPD_SDRAM_WIDTH]) & 0x7F); LoadNum = (u8) (ModuleDataWidth / ChipWidth); - /*set the RANK map */ - RankNum = (u8) (pSPDDataBuf[SPD_SDRAM_DIMM_RANKS] & 0x3); /*get bit0,1, the Most number of supported RANK is 2 */ + /* Set the RANK map. */ + /* Get bit0,1, the most number of supported RANK is 2. */ + RankNum = (u8) (pSPDDataBuf[SPD_SDRAM_DIMM_RANKS] & 0x3); if (RAMTYPE_SDRAMDDR2 == DramAttr->DramType) - RankNum++; /*for DDR bit[0,1] 01->1 RANK 10->2 RANK; for DDR2 bit[0,1] = 00 -> 1 RANK 01 -> 2 RANK */ - if (RankNum != 2 && RankNum != 1) { /*every DIMM have 1 or 2 ranks */ + /* + * For DDR bit[0,1]: 01->1 RANK, 10->2 RANK + * For DDR2 bit[0,1]: 00->1 RANK, 01->2 RANK + */ + RankNum++; + + /* Every DIMM have 1 or 2 ranks. */ + if (RankNum != 2 && RankNum != 1) { Status = CB_DEVICE_ERROR; - PRINT_DEBUG_MEM - ("Memory Device ERROR: the number of RANK not support!\r"); + PRINT_DEBUG_MEM("Memory Device ERROR: Number " + "of RANK not supported!\r"); break; } - if (Sockets < 2) { /*sockets0,1 is channel A */ + if (Sockets < 2) { /* Sockets0,1 is channel A */ DramAttr->RankNumChA = (u8) (DramAttr->RankNumChA + RankNum); DramAttr->DimmNumChA++; DramAttr->LoadNumChA = (u8) (DramAttr->LoadNumChA * LoadNum * RankNum); - } else { /*sockets2,3 is channel B */ - + } else { /* Sockets2,3 is channel B */ DramAttr->RankNumChB = (u8) (DramAttr->RankNumChB + RankNum); DramAttr->DimmNumChB++; @@ -175,12 +182,12 @@ CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR * DramAttr) (u8) (DramAttr->LoadNumChB * LoadNum * RankNum);; } - RankNum |= 1; /*set rank map */ - DramAttr->RankPresentMap |= - (RankNum << (Sockets * 2)); + RankNum |= 1; /* Set rank map. */ + DramAttr->RankPresentMap |= (RankNum << (Sockets * 2)); bFind = TRUE; } } + PRINT_DEBUG_MEM("Rank Present Map:"); PRINT_DEBUG_MEM_HEX8(DramAttr->RankPresentMap); PRINT_DEBUG_MEM("\r"); diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c index bb0232589d..390d2a993c 100644 --- a/src/northbridge/via/vx800/dev_init.c +++ b/src/northbridge/via/vx800/dev_init.c @@ -17,21 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -void DRAMSetVRNum(DRAM_SYS_ATTR * DramAttr, u8 PhyRank, // Physical Rank - u8 VirRank, // Virtual Rank - BOOLEAN Enable); - -void SetEndingAddr(DRAM_SYS_ATTR * DramAttr, u8 VirRank, // Ending address register number indicator (INDEX - INT8 Value // (value) add or subtract value to this and after banks - ); - -void InitDDR2CHA(DRAM_SYS_ATTR * DramAttr); - -void InitDDR2CHB(DRAM_SYS_ATTR * DramAttr); - -void InitDDR2CHC(DRAM_SYS_ATTR * DramAttr); +void DRAMSetVRNum(DRAM_SYS_ATTR *DramAttr, u8 PhyRank /* physical rank */, + u8 VirRank /* virtual rank */, BOOLEAN Enable); +void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank /* Ending address + register number indicator (INDEX */, INT8 Value /* (value) + add or subtract value to this and after banks. */); +void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr); +void InitDDR2CHB(DRAM_SYS_ATTR *DramAttr); +void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr); CB_STATUS VerifyChc(); + /*=================================================================== Function : DRAMRegInitValue() Precondition : @@ -43,7 +39,7 @@ Purpose : Set necessary register before DRAM initialize ===================================================================*/ static const u8 DramRegTbl[][3] = { - //Register AND OR + /* Reg AND OR */ {0x50, 0x11, 0xEE}, // DDR default MA7 for DRAM init {0x51, 0x11, 0x60}, // DDR default MA3 for CHB init {0x52, 0x00, 0x33}, // DDR use BA0=M17, BA1=M18, @@ -56,26 +52,31 @@ static const u8 DramRegTbl[][3] = { {0x60, 0x00, 0x00}, // disable fast turn-around {0x65, 0x00, 0xD9}, // AGP timer = 0XD; Host timer = 8; - {0x66, 0x00, 0x88}, //DRAMC Queue Size = 4; park at the last bus owner,Priority promotion timer = 8 + {0x66, 0x00, 0x88}, // DRAMC Queue Size = 4; park at the last bus + // owner,Priority promotion timer = 8 {0x68, 0x00, 0x0C}, {0x69, 0xF0, 0x04}, // set RX69[3:0]=0000b {0x6A, 0x00, 0x00}, // refresh counter - {0x6E, 0xF8, 0x80}, //must set 6E[7],or else DDR2 probe test will fail - // In here, we not set RX70~RX74, because we just init DRAM but no need R/W DRAM, - // when we check DQS input/output delay, then we need R/W DRAM. - - //{0x79, 0x00, 0x8F }, + {0x6E, 0xF8, 0x80}, // must set 6E[7], or else DDR2 probe test + // will fail + /* + * In here, we not set RX70~RX74, because we just init DRAM but no + * need R/W DRAM, when we check DQS input/output delay, then we need + * R/W DRAM. + */ + + // {0x79, 0x00, 0x8F }, {0x85, 0x00, 0x00}, - // {0x90, 0x87, 0x78 }, - // {0x91, 0x00, 0x46 }, + // {0x90, 0x87, 0x78 }, + // {0x91, 0x00, 0x46 }, {0x40, 0x00, 0x00}, + {0, 0, 0} }; -void DRAMRegInitValue(DRAM_SYS_ATTR * DramAttr) +void DRAMRegInitValue(DRAM_SYS_ATTR *DramAttr) { - u8 Idx, CL; - u8 Data; + u8 Idx, CL, Data; for (Idx = 0; DramRegTbl[Idx][0] != 0; Idx++) { Data = pci_read_config8(MEMCTRL, DramRegTbl[Idx][0]); @@ -87,68 +88,69 @@ void DRAMRegInitValue(DRAM_SYS_ATTR * DramAttr) Data = 0x80; pci_write_config8(PCI_DEV(0, 0, 4), 0xa3, Data); - //set Dram Controllor mode + // Set DRAM controller mode. */ Data = pci_read_config8(MEMCTRL, 0x6c); Data &= 0xFB; if (ENABLE_CHC == 0) { - Data |= 0x4; //only CHA 64 bit mode + Data |= 0x4; /* Only CHA 64 bit mode */ pci_write_config8(MEMCTRL, 0x6c, Data); } else { - Data |= 0x0; //CHA + CHC + Data |= 0x0; /* CHA + CHC */ pci_write_config8(MEMCTRL, 0x6c, Data); - //Data = 0xAA; - //pci_write_config8(MEMCTRL, 0xb1, Data); + // Data = 0xAA; + // pci_write_config8(MEMCTRL, 0xb1, Data); - //set CHB DQSB input delay, or else will meet error which is some byte is right - //but another bit is error + // set CHB DQSB input delay, or else will meet error which + // is some byte is right but another bit is error. Data = pci_read_config8(MEMCTRL, 0xff); Data = (Data & 0x03) | 0x3D; pci_write_config8(MEMCTRL, 0xff, Data); - //enable CHC RXDB[7] - //Data=pci_read_config8(MEMCTRL, 0xdb); - // Data = (Data & 0x7F) | 0x80; - //pci_write_config8(MEMCTRL, 0xdb, Data); + // enable CHC RXDB[7] + // Data = pci_read_config8(MEMCTRL, 0xdb); + // Data = (Data & 0x7F) | 0x80; + // pci_write_config8(MEMCTRL, 0xdb, Data); - //rx62[2:0],CHA and CHB CL + // rx62[2:0], CHA and CHB CL Data = pci_read_config8(MEMCTRL, 0x62); CL = Data & 0x07; - //if CL = 6 , so I set CHB CL = 5 default + // If CL = 6, so I set CHB CL = 5 default. if (CL >= 4) CL = 3; - // set CHC Read CL rxDC[6:7] + /* Set CHC Read CL rxDC[6:7]. */ Data = pci_read_config8(MEMCTRL, 0xdc); Data = (Data & 0x3F) | (CL << 6); pci_write_config8(MEMCTRL, 0xdc, Data); - // set CHC write CL rxDF[6:7] + + /* Set CHC write CL rxDF[6:7]. */ Data = pci_read_config8(MEMCTRL, 0xdf); Data = (Data & 0x3F) | (CL << 6); pci_write_config8(MEMCTRL, 0xdf, Data); - // set CHC ODT RxDC[5:0] + + /* Set CHC ODT RxDC[5:0] */ Data = pci_read_config8(MEMCTRL, 0xdc); Data = (Data & 0xC0) | 0x03; pci_write_config8(MEMCTRL, 0xdc, Data); - //set column type RXDD[6] and enable ODT PAD RXDD[7] + /* Set column type RXDD[6] and enable ODT PAD RXDD[7]. */ Data = pci_read_config8(MEMCTRL, 0xdd); Data |= 0x80; Idx = DramAttr->DimmInfo[2].SPDDataBuf[SPD_SDRAM_COL_ADDR]; if ((Idx & 0x0F) == 10) - Data |= 0x40; //MA9~MA0 + Data |= 0x40; /* MA9~MA0 */ else - Data &= 0xBF; //MA8~MA0 + Data &= 0xBF; /* MA8~MA0 */ pci_write_config8(MEMCTRL, 0xdd, Data); } - // Disable read DRAM fast ready ;Rx51[7] - // Disable Read Around Write ;Rx51[6] - - // Disable Consecutive Read ;RX52[1:0] - // disable speculative read + // Disable Read DRAM fast ready ;Rx51[7] + // Disable Read Around Write ;Rx51[6] + // Disable Consecutive Read ;RX52[1:0] + // Disable Speculative Read } /*=================================================================== @@ -163,18 +165,18 @@ Purpose : DRAM initialize according to the bios porting guid #define EXIST_TEST_PATTERN 0x55555555 #define NOT_EXIST_TEST_PATTERN 0xAAAAAAAA -BOOLEAN ChkForExistLowBank() + +BOOLEAN ChkForExistLowBank(void) { u32 *Address, data32; - // Check Pattern - + /* Check pattern */ Address = (u32 *) 8; *Address = EXIST_TEST_PATTERN; Address = (u32 *) 4; *Address = EXIST_TEST_PATTERN; -// _asm {WBINVD} + // _asm {WBINVD} WaitMicroSec(100); Address = (u32 *) 8; data32 = *Address; @@ -185,15 +187,14 @@ BOOLEAN ChkForExistLowBank() if (data32 != EXIST_TEST_PATTERN) return FALSE; - // Check not Pattern + /* Check not Pattern */ Address = (u32 *) 8; *Address = NOT_EXIST_TEST_PATTERN; Address = (u32 *) 4; *Address = NOT_EXIST_TEST_PATTERN; - //_asm {WBINVD} + // _asm {WBINVD} WaitMicroSec(100); - Address = (u32 *) 8; data32 = *Address; if (data32 != (u32) (NOT_EXIST_TEST_PATTERN)) @@ -206,9 +207,10 @@ BOOLEAN ChkForExistLowBank() return TRUE; } -void InitDDR2CHC(DRAM_SYS_ATTR * DramAttr); -void InitDDR2CHB(DRAM_SYS_ATTR * DramAttr); -void DRAMInitializeProc(DRAM_SYS_ATTR * DramAttr) +void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr); +void InitDDR2CHB(DRAM_SYS_ATTR *DramAttr); + +void DRAMInitializeProc(DRAM_SYS_ATTR *DramAttr) { u8 shift, idx; BOOLEAN Status; @@ -216,11 +218,14 @@ void DRAMInitializeProc(DRAM_SYS_ATTR * DramAttr) shift = 1; for (idx = 0; idx < MAX_RANKS; idx++) { if ((DramAttr->RankPresentMap & shift) != 0) { - // Set VR# to physical rank indicated = PR + physical rank enable bit + /* + * Set VR# to physical rank indicated = PR + physical + * rank enable bit. + */ DRAMSetVRNum(DramAttr, idx, idx, TRUE); - SetEndingAddr(DramAttr, idx, 0x10); // assume 1G size - if (idx < 4) //CHA init - InitDDR2CHA(DramAttr); //temp wjb 2007/1 only for compiling + SetEndingAddr(DramAttr, idx, 0x10); /* Assume 1G size */ + if (idx < 4) /* CHA init */ + InitDDR2CHA(DramAttr); // temp wjb 2007/1 only for compiling // in the function InitDDR2,the parameter is no need Status = ChkForExistLowBank(); if (Status == TRUE) { @@ -228,7 +233,11 @@ void DRAMInitializeProc(DRAM_SYS_ATTR * DramAttr) } else { PRINT_DEBUG_MEM(" F\r"); } - // Set VR# to physical rank indicated = 00h + physical rank enable bit + + /* + * Set VR# to physical rank indicated = 00h + physical + * rank enable bit. + */ DRAMSetVRNum(DramAttr, idx, 0, FALSE); SetEndingAddr(DramAttr, idx, -16); } @@ -239,7 +248,6 @@ void DRAMInitializeProc(DRAM_SYS_ATTR * DramAttr) } - /*=================================================================== Function : DRAMSetVRNUM() Precondition : @@ -255,12 +263,11 @@ Purpose : Set virtual rank number for physical rank Program when necessary, otherwise don't touch the pr-vr-mapping registers ===================================================================*/ -void DRAMSetVRNum(DRAM_SYS_ATTR * DramAttr, u8 PhyRank, // Physical Rank - u8 VirRank, // Virtual Rank - BOOLEAN Enable) +void DRAMSetVRNum(DRAM_SYS_ATTR *DramAttr, u8 PhyRank /* physical rank */, + u8 VirRank /* virtual rank */, BOOLEAN Enable) { - u8 Data; - u8 AndData, OrData; + u8 Data, AndData, OrData; + Data = pci_read_config8(MEMCTRL, (0x54 + (PhyRank >> 1))); OrData = 0; @@ -268,17 +275,17 @@ void DRAMSetVRNum(DRAM_SYS_ATTR * DramAttr, u8 PhyRank, // Physical Rank OrData |= 0x08; OrData |= VirRank; if ((PhyRank & 0x01) == 0x00) { - AndData = 0x0F; // keep the value of odd rank on PR # is even(keep 1,3,5,7) + AndData = 0x0F; // keep the value of odd rank on PR # is even(keep 1,3,5,7) OrData <<= 4; // VR #, value to be set } else { AndData = 0xF0; // keep the value of even rank on PR # is odd(keep 0,2,4,6) } + Data &= AndData; Data |= OrData; pci_write_config8(MEMCTRL, (0x54 + (PhyRank >> 1)), Data); } - /*=================================================================== Function : SetEndingAddr() Precondition : @@ -291,17 +298,17 @@ Output : Void Purpose : Set ending address of virtual rank specified by VirRank ===================================================================*/ -void SetEndingAddr(DRAM_SYS_ATTR * DramAttr, u8 VirRank, // Ending address register number indicator (INDEX - INT8 Value // (value) add or subtract value to this and after banks - ) { +void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank, /* ending address + register number indicator (INDEX */, INT8 Value /* (value) + add or subtract value to this and after banks */) { u8 Data; - // Read register,Rx40-Rx47(0,1,2,3,4,5,6,7) and set the ending address + /* Read register,Rx40-Rx47(0,1,2,3,4,5,6,7) and set ending address. */ Data = pci_read_config8(MEMCTRL, 0x40 + VirRank); Data = (u8) (Data + Value); pci_write_config8(MEMCTRL, 0x40 + VirRank, Data); - //program the virank's begining address to zero + /* Program the virank's begining address to zero. */ Data = 0x00; pci_write_config8(MEMCTRL, 0x48 + VirRank, Data); } @@ -335,48 +342,51 @@ static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 #define CHA_MRS_DDR2_TWR6 (1 << 13) + (0 << 20) + (1 << 12) // Value = 003000h // DDR2 Twr=2 Twr=3 Twr=4 Twr=5 -static const u32 CHA_DDR2_Twr_table[5] = - { CHA_MRS_DDR2_TWR2, CHA_MRS_DDR2_TWR3, CHA_MRS_DDR2_TWR4, -CHA_MRS_DDR2_TWR5, CHA_MRS_DDR2_TWR6 }; +static const u32 CHA_DDR2_Twr_table[5] = { + CHA_MRS_DDR2_TWR2, CHA_MRS_DDR2_TWR3, CHA_MRS_DDR2_TWR4, + CHA_MRS_DDR2_TWR5, CHA_MRS_DDR2_TWR6 +}; #define CHA_OCD_Exit_150ohm 0x20200 // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=1,MA2=0 (DRAM bus address) // A17=1, A12=A11=A10=0,A9=1 ,A5=0 (CPU address) -#define CHA_OCD_Default_150ohm 0x21E00 // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=1,MA2=0 (DRAM bus address) +#define CHA_OCD_Default_150ohm 0x21E00 // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=1,MA2=0 (DRAM bus address) // A17=1, A12=A11=A10=1,A9=1 ,A5=0 (CPU address) #define CHA_OCD_Exit_75ohm 0x20020 // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=0,MA2=1 (DRAM bus address) // A17=1, A12=A11=A10=0,A9=0 ,A5=1 (CPU address) -#define CHA_OCD_Default_75ohm 0x21C20 // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=0,MA2=1 (DRAM bus address) +#define CHA_OCD_Default_75ohm 0x21C20 // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=0,MA2=1 (DRAM bus address) // A17=1, A12=A11=A10=1,A9=0 ,A5=1 (CPU address) -void InitDDR2CHA(DRAM_SYS_ATTR * DramAttr) +void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr) { - u8 Data; - u8 Reg6BVal; - u8 Idx, CL, BL, Twr; + u8 Data, Reg6BVal, Idx, CL, BL, Twr, DimmNum; u32 AccessAddr; - u8 DimmNum; - // step2. - //disable bank paging and multi page + /* Step 2 */ + /* Disable bank paging and multi page. */ Data = pci_read_config8(MEMCTRL, 0x69); Data &= ~0x03; pci_write_config8(MEMCTRL, 0x69, Data); Reg6BVal = pci_read_config8(MEMCTRL, 0x6b); Reg6BVal &= ~0x07; - // Step 3. - // At least one NOP cycle will be issued after the 1m sec device deselect. + + /* Step 3 */ + /* At least one NOP cycle will be issued after the 1m sec device + * deselect. + */ Data = Reg6BVal | 0x01; pci_write_config8(MEMCTRL, 0x6b, Data); - // step4. - //Read a double word from any address of the DIMM + /* Step 4 */ + /* Read a double word from any address of the DIMM. */ DimmRead(0x0); - // Step 5. - // A minimum pause of 200u sec will be provided after the NOP. - // - <<< reduce BOOT UP time >>> - - // Loop 200us + /* Step 5 */ + /* + * A minimum pause of 200u sec will be provided after the NOP. + * - <<< reduce BOOT UP time >>> - + * Loop 200us + */ for (Idx = 0; Idx < 0x10; Idx++) WaitMicroSec(100); @@ -386,7 +396,7 @@ void InitDDR2CHA(DRAM_SYS_ATTR * DramAttr) pci_write_config8(MEMCTRL, 0x6b, Data); // Step7. - //Read a double word from any address of the DIMM + // Read a double word from any address of the DIMM DimmRead(0x0); // Step 8. @@ -394,48 +404,46 @@ void InitDDR2CHA(DRAM_SYS_ATTR * DramAttr) Data = Reg6BVal | 0x03; pci_write_config8(MEMCTRL, 0x6b, Data); - - // Step 9,10. check ODT value for EMRS(1) command - // according to ODTLookUp_TBL in driving_setting.c if there is one dimm in MB's one channel , the DDR2's ODT is 150ohm - // if there is two dimm in MB's one channel, the DDR2's ODT is 75 ohm + /* Step 9, 10. + * + * Check ODT value for EMRS(1) command according to ODTLookUp_TBL + * in driving_setting.c if there is one DIMM in MB's one channel, + * the DDR2's ODT is 150ohm if there is two DIMM in MB's one channel, + * the DDR2's ODT is 75 ohm. + */ DimmNum = DramAttr->DimmNumChA; - if (DimmNum == 1) //DDR's ODT is 150ohm - { + if (DimmNum == 1) { /* DDR's ODT is 150ohm */ AccessAddr = (u32) CHA_MRS_DLL_150[0]; - DimmRead(AccessAddr); //issue EMRS DLL Enable + DimmRead(AccessAddr); /* Issue EMRS DLL Enable. */ PRINT_DEBUG_MEM("Step 9 Address "); PRINT_DEBUG_MEM_HEX32(AccessAddr); PRINT_DEBUG_MEM("\r"); AccessAddr = (u32) CHA_MRS_DLL_150[1]; - DimmRead(AccessAddr); //issue MRS DLL Reset + DimmRead(AccessAddr); /* Issue MRS DLL Reset. */ PRINT_DEBUG_MEM("Step 10 Address "); PRINT_DEBUG_MEM_HEX32(AccessAddr); PRINT_DEBUG_MEM("\r"); - } else if (DimmNum == 2) //DDR's ODT is 75ohm - { + } else if (DimmNum == 2) { /* DDR's ODT is 75ohm */ AccessAddr = (u32) CHA_MRS_DLL_75[0]; - DimmRead(AccessAddr); //issue EMRS DLL Enable + DimmRead(AccessAddr); /* Issue EMRS DLL Enable. */ AccessAddr = (u32) CHA_MRS_DLL_75[1]; - DimmRead(AccessAddr); //issue MRS DLL Reset + DimmRead(AccessAddr); /* Issue MRS DLL Reset. */ } else { PRINT_DEBUG_MEM("Dimm NUM ERROR:"); PRINT_DEBUG_MEM_HEX8(DimmNum); PRINT_DEBUG_MEM("\r"); } - // Step 11. - // Precharge all (PALL) will be issued to the DDR. + /* Step 11. Precharge all (PALL) will be issued to the DDR. */ Data = Reg6BVal | 0x02; pci_write_config8(MEMCTRL, 0x6b, Data); - // Step12. - //Read a double word from any address of the DIMM + /* Step 12. Read a double word from any address of the DIMM. */ DimmRead(0x0); - // Step 13. - // Execute 8 CBR refresh + /* Step 13. Execute 8 CBR refresh. */ Data = Reg6BVal | 0x04; pci_write_config8(MEMCTRL, 0x6b, Data); @@ -446,70 +454,70 @@ void InitDDR2CHA(DRAM_SYS_ATTR * DramAttr) WaitMicroSec(100); } - // Step 17. - // enable MRS for MAA + /* Step 17. Enable MRS for MAA. */ Data = Reg6BVal | 0x03; pci_write_config8(MEMCTRL, 0x6b, Data); - //Step 18 - //the SDRAM parameters.(Burst Length, CAS# Latency , Write recovery etc.) - //------------------------------------------------------------- - //Burst Length : really offset Rx6c[3] + /* + * Step 18. The SDRAM parameters (Burst Length, CAS# Latency, + * Write recovery etc.) + */ + + /* Burst Length: really offset Rx6c[3] */ Data = pci_read_config8(MEMCTRL, 0x6c); BL = (Data & 0x08) >> 3; - // CL = really offset RX62[2:0] + /* CL: really offset RX62[2:0] */ Data = pci_read_config8(MEMCTRL, 0x62); CL = Data & 0x03; AccessAddr = (u32) (CHA_DDR2_MRS_table[CL]); - if (BL) { + if (BL) AccessAddr += 8; - } - //Write recovery : really offset Rx63[7-5] + + /* Write recovery: really offset Rx63[7-5] */ Data = pci_read_config8(MEMCTRL, 0x63); Twr = (Data & 0xE0) >> 5; AccessAddr += CHA_DDR2_Twr_table[Twr]; // AccessAddr = 0x1012D8; - DimmRead(AccessAddr); // Set MRS command + DimmRead(AccessAddr); /* Set MRS command. */ PRINT_DEBUG_MEM("Step 18 Address"); PRINT_DEBUG_MEM_HEX32(AccessAddr); PRINT_DEBUG_MEM("\r"); - //Step 19,20 - if (DimmNum == 1) //DDR's ODT is 150ohm - { + /* Step 19, 20 */ + if (DimmNum == 1) { /* DDR's ODT is 150ohm */ AccessAddr = (u32) CHA_OCD_Default_150ohm; - DimmRead(AccessAddr); //issue EMRS OCD Default + DimmRead(AccessAddr); /* Issue EMRS OCD Default. */ PRINT_DEBUG_MEM("Step 19 Address "); PRINT_DEBUG_MEM_HEX32(AccessAddr); PRINT_DEBUG_MEM("\r"); AccessAddr = (u32) CHA_OCD_Exit_150ohm; - DimmRead(AccessAddr); //issue EMRS OCD Calibration Mode Exit + DimmRead(AccessAddr); /* Issue EMRS OCD Calibration Mode Exit. */ PRINT_DEBUG_MEM("Step 20 Address "); PRINT_DEBUG_MEM_HEX32(AccessAddr); PRINT_DEBUG_MEM("\r"); - } else if (DimmNum == 2) //DDR's ODT is 75ohm - { + } else if (DimmNum == 2) { /* DDR's ODT is 75ohm */ AccessAddr = (u32) CHA_OCD_Default_75ohm; - DimmRead(AccessAddr); //issue EMRS OCD Default + DimmRead(AccessAddr); /* Issue EMRS OCD Default. */ AccessAddr = (u32) CHA_OCD_Exit_75ohm; - DimmRead(AccessAddr); //issue EMRS OCD Calibration Mode Exit + DimmRead(AccessAddr); /* Issue EMRS OCD Calibration Mode Exit. */ } else { PRINT_DEBUG_MEM("Dimm NUM ERROR: "); PRINT_DEBUG_MEM_HEX8(DimmNum); PRINT_DEBUG_MEM("\r"); } - //Step 21 - //After MRS the device should be ready for full functionality within 3 clocks - // after Tmrd is met. + /* + * Step 21. After MRS the device should be ready for full + * functionality within 3 clocks after Tmrd is met. + */ Data = Reg6BVal; pci_write_config8(MEMCTRL, 0x6b, Data); - // Enable bank paging and multi page + /* Enable bank paging and multi page. */ Data = pci_read_config8(MEMCTRL, 0x69); Data |= 0x03; pci_write_config8(MEMCTRL, 0x69, Data); @@ -593,7 +601,6 @@ void InitDDR2CHB( Data |= 0x80; pci_write_config8(MEMCTRL, 0xd3, Data); - // Step 7. // A minimum pause of 200u sec will be provided after the NOP. // - <<< reduce BOOT UP time >>> - @@ -657,7 +664,6 @@ void InitDDR2CHB( Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data); - //step 14. MSR DLL Reset AccessAddr = CHB_MRS_DLL_150[1] >> 3; Data =(u8) (AccessAddr & 0xff); @@ -727,7 +733,6 @@ void InitDDR2CHB( Data |= 0x00; pci_write_config8(MEMCTRL, 0xd3, Data); - //the SDRAM parameters.(Burst Length, CAS# Latency , Write recovery etc.) //------------------------------------------------------------- @@ -739,7 +744,6 @@ void InitDDR2CHB( Data=pci_read_config8(MEMCTRL, 0x62); CL = Data & 0x03; - AccessAddr = (u32)(CHB_DDR2_MRS_table[CL]); if (BL) { @@ -798,7 +802,6 @@ void InitDDR2CHB( Data |= (u8)((AccessAddr & 0x30000) >> 15); pci_write_config8(MEMCTRL, 0xd7, Data); - //step 27. issue EMRS cycle Data=pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; @@ -848,7 +851,6 @@ void InitDDR2CHB( Data &= 0xF9; pci_write_config8(MEMCTRL, 0xd7, Data); - //step 30. normal SDRAM Mode Data=pci_read_config8(MEMCTRL, 0xd7); Data &= 0xC7; @@ -872,6 +874,7 @@ void InitDDR2CHB( pci_write_config8(MEMCTRL, 0x69, Data); } */ + /*=================================================================== Function : InitDDR2CHC() Precondition : @@ -885,132 +888,128 @@ Reference : // DDR2 CL=2 CL=3 CL=4 CL=5 (Burst type=interleave)(WR fine tune in code) static const u16 CHC_MRS_table[4] = { 0x22B, 0x23B, 0x24B, 0x25B }; // Use 1X-bandwidth MA table to init DRAM -void InitDDR2CHC(DRAM_SYS_ATTR * DramAttr) +void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr) { - u8 Data; - u8 Idx, CL, Twr; + u8 Data, Idx, CL, Twr; u32 AccessAddr; CB_STATUS Status; - // step3. - //clear RxDF[2] to disable Tri-state output + /* Step 3. Clear RxDF[2] to disable Tri-state output. */ Data = pci_read_config8(MEMCTRL, 0xdf); Data &= 0xFB; pci_write_config8(MEMCTRL, 0xdf, Data); - - - //step 4. Enable the initialization mode of DRAM Controller C with NB's PLL clock + /* + * Step 4. Enable the initialization mode of DRAM Controller C with + * NB's PLL clock. + */ Data = pci_read_config8(MEMCTRL, 0xdb); Data |= 0x60; pci_write_config8(MEMCTRL, 0xdb, Data); - //Step 5. NOP command enable + /* Step 5. NOP command enable. */ Data = pci_read_config8(MEMCTRL, 0xdb); Data &= 0xE3; Data |= 0x00; pci_write_config8(MEMCTRL, 0xdb, Data); - - //Step 6. issue a nop cycle,RegDB[1] 0 -> 1 + /* Step 6. Issue a nop cycle, RegDB[1] 0 -> 1. */ Data = pci_read_config8(MEMCTRL, 0xdb); Data |= 0x2; pci_write_config8(MEMCTRL, 0xdb, Data); Data &= 0xFD; pci_write_config8(MEMCTRL, 0xdb, Data); - - // Step 7. - // A minimum pause of 200u sec will be provided after the NOP. - // - <<< reduce BOOT UP time >>> - - // Loop 200us + /* + * Step 7. + * A minimum pause of 200u sec will be provided after the NOP. + * - <<< reduce BOOT UP time >>> - + * Loop 200us + */ for (Idx = 0; Idx < 0x10; Idx++) WaitMicroSec(100); - // Step 8. - // signal bank precharge command enable + /* Step 8. Signal bank precharge command enable. */ Data = pci_read_config8(MEMCTRL, 0xdb); Data &= 0xE3; Data |= 0x14; pci_write_config8(MEMCTRL, 0xdb, Data); - //set MA10 =1, precharge all bank + /* Set MA10 = 1, precharge all bank. */ Data = 0x00; pci_write_config8(MEMCTRL, 0xf8, Data); - Data = 0x04; pci_write_config8(MEMCTRL, 0xf9, Data); - //step 9. issue a precharge all cycle,RegD3[7] 0 -> 1 + /* step 9. Issue a precharge all cycle, RegD3[7] 0 -> 1. */ Data = pci_read_config8(MEMCTRL, 0xdb); Data |= 0x2; pci_write_config8(MEMCTRL, 0xdb, Data); Data &= 0xFD; pci_write_config8(MEMCTRL, 0xdb, Data); - //step10. MRS enable + /* Step 10. MRS enable. */ Data = pci_read_config8(MEMCTRL, 0xdb); Data &= 0xE3; Data |= 0x1C; pci_write_config8(MEMCTRL, 0xdb, Data); - - //step11. EMRS DLL enable and Disable DQS + /* Step 11. EMRS DLL enable and Disable DQS. */ Data = 0x40; pci_write_config8(MEMCTRL, 0xf8, Data); Data = 0x24; pci_write_config8(MEMCTRL, 0xf9, Data); - //step12. issue EMRS cycle + /* Step 12. Issue EMRS cycle. */ Data = pci_read_config8(MEMCTRL, 0xdb); Data |= 0x2; pci_write_config8(MEMCTRL, 0xdb, Data); Data &= 0xFD; pci_write_config8(MEMCTRL, 0xdb, Data); - //step13. MSR enable + /* Step 13. MSR enable. */ Data = pci_read_config8(MEMCTRL, 0xdb); Data &= 0xE3; Data |= 0x1C; pci_write_config8(MEMCTRL, 0xdb, Data); - //step 14. MSR DLL Reset + /* Step 14. MSR DLL Reset. */ Data = 0x00; pci_write_config8(MEMCTRL, 0xf8, Data); Data = 0x01; pci_write_config8(MEMCTRL, 0xf9, Data); - //step15. issue MRS cycle + /* Step 15. Issue MRS cycle. */ Data = pci_read_config8(MEMCTRL, 0xdb); Data |= 0x2; pci_write_config8(MEMCTRL, 0xdb, Data); Data &= 0xFD; pci_write_config8(MEMCTRL, 0xdb, Data); - //step16. signal banks precharge command enable + /* Step 16. Signal banks precharge command enable. */ Data = pci_read_config8(MEMCTRL, 0xdb); Data &= 0xE3; Data |= 0x14; pci_write_config8(MEMCTRL, 0xdb, Data); - //set MA10 =1, precharge all bank + /* Set MA10 = 1, precharge all bank. */ Data = 0x00; pci_write_config8(MEMCTRL, 0xf8, Data); Data = 0x04; pci_write_config8(MEMCTRL, 0xf9, Data); - // step17. issue precharge all cycle + /* Step 17. Issue precharge all cycle. */ Data = pci_read_config8(MEMCTRL, 0xdb); Data |= 0x2; pci_write_config8(MEMCTRL, 0xdb, Data); Data &= 0xFD; pci_write_config8(MEMCTRL, 0xdb, Data); - //step18. CBR cycle enable + /* Step 18. CBR cycle enable. */ Data = pci_read_config8(MEMCTRL, 0xdb); Data &= 0xE3; Data |= 0x18; @@ -1075,7 +1074,6 @@ void InitDDR2CHC(DRAM_SYS_ATTR * DramAttr) Data |= 0x1C; pci_write_config8(MEMCTRL, 0xdb, Data); - //step 26. OCD default Data = 0xC0; pci_write_config8(MEMCTRL, 0xf8, Data); @@ -1097,7 +1095,6 @@ void InitDDR2CHC(DRAM_SYS_ATTR * DramAttr) Data = 0x24; pci_write_config8(MEMCTRL, 0xf9, Data); - //step 29. issue EMRS cycle Data = pci_read_config8(MEMCTRL, 0xdb); Data |= 0x2; @@ -1114,7 +1111,7 @@ void InitDDR2CHC(DRAM_SYS_ATTR * DramAttr) pci_write_config8(MEMCTRL, 0xdb, Data); } -CB_STATUS VerifyChc() +CB_STATUS VerifyChc(void) { u8 Data, ByteVal, Index, pad; u16 row; @@ -1125,18 +1122,15 @@ CB_STATUS VerifyChc() //verify each MA[0:12],BA[0:1] pad = 1; for (row = 0; row < 0x8000; row++) { - //set the write value; - //verify each MD[15:0] + /* Set the write value, Verify each MD[15:0]. */ for (Data = pad, Index = 0; Index < 16; Index++) { Data <<= 1; if (Data == 0) Data = 1; - pci_write_config8(PCI_DEV(0, 0, 7), 0xC0 + Index, - Data); - + pci_write_config8(PCI_DEV(0, 0, 7), 0xC0 + Index, Data); } - //issue the bank active command + /* Issue the bank active command. */ // bank active command enable Data = pci_read_config8(MEMCTRL, 0xdb); Data &= 0xE3; @@ -1149,14 +1143,14 @@ CB_STATUS VerifyChc() Data = (u8) ((row && 0xFF) >> 8); pci_write_config8(MEMCTRL, 0xf9, Data); - // issue active cycle + /* Issue active cycle. */ Data = pci_read_config8(MEMCTRL, 0xdb); Data |= 0x2; pci_write_config8(MEMCTRL, 0xdb, Data); Data &= 0xFD; pci_write_config8(MEMCTRL, 0xdb, Data); - //issue ready/completion for read/write + /* Issue ready/completion for read/write. */ // read/completion command enable Data = pci_read_config8(MEMCTRL, 0xdb); Data &= 0xE3; @@ -1169,14 +1163,14 @@ CB_STATUS VerifyChc() Data = 0x00; pci_write_config8(MEMCTRL, 0xf9, Data); - // issue read/completion cycle + /* Issue read/completion cycle. */ Data = pci_read_config8(MEMCTRL, 0xdb); Data |= 0x2; pci_write_config8(MEMCTRL, 0xdb, Data); Data &= 0xFD; pci_write_config8(MEMCTRL, 0xdb, Data); - //issue write command + /* Issue write command. */ // write command enable Data = pci_read_config8(MEMCTRL, 0xdb); Data &= 0xE3; @@ -1189,7 +1183,7 @@ CB_STATUS VerifyChc() Data = (u8) ((row & 0x60) << 5); pci_write_config8(MEMCTRL, 0xf9, Data); - // issue write cycle + /* Issue write cycle. */ Data = pci_read_config8(MEMCTRL, 0xdb); Data |= 0x2; pci_write_config8(MEMCTRL, 0xdb, Data); @@ -1209,14 +1203,14 @@ CB_STATUS VerifyChc() Data = 0x00; pci_write_config8(MEMCTRL, 0xf9, Data); - // issue read/completion cycle + /* Issue read/completion cycle. */ Data = pci_read_config8(MEMCTRL, 0xdb); Data |= 0x2; pci_write_config8(MEMCTRL, 0xdb, Data); Data &= 0xFD; pci_write_config8(MEMCTRL, 0xdb, Data); - //issue the bank active command + /* Issue the bank active command. */ // bank active command enable Data = pci_read_config8(MEMCTRL, 0xdb); Data &= 0xE3; @@ -1289,21 +1283,19 @@ CB_STATUS VerifyChc() Data = 0x00; pci_write_config8(MEMCTRL, 0xf9, Data); - // issue read/completion cycle + /* Issue read/completion cycle. */ Data = pci_read_config8(MEMCTRL, 0xdb); Data |= 0x2; pci_write_config8(MEMCTRL, 0xdb, Data); Data &= 0xFD; pci_write_config8(MEMCTRL, 0xdb, Data); - //verify the value; + /* Verify the value. */ for (ByteVal = pad, Index = 0; Index < 16; Index++) { - Data = - pci_read_config8(PCI_DEV(0, 0, 7), - 0xD0 + Index); + Data = pci_read_config8(PCI_DEV(0, 0, 7), 0xD0 + Index); if (ByteVal != Data) { - PRINT_DEBUG_MEM - ("error!!!! row = %x,Index =%x,Data = %x,ByteVal=%x\r"); + PRINT_DEBUG_MEM("Error! row = %x, index =%x, " + "data = %x, byteval=%x\r"); } ByteVal <<= 1; if (ByteVal == 0) diff --git a/src/northbridge/via/vx800/dqs_search.c b/src/northbridge/via/vx800/dqs_search.c index 80749f8597..785d775baf 100644 --- a/src/northbridge/via/vx800/dqs_search.c +++ b/src/northbridge/via/vx800/dqs_search.c @@ -74,7 +74,6 @@ void SetDQSOutputCHA(DRAM_SYS_ATTR * DramAttr) pci_write_config8(MEMCTRL, 0x71, Reg71); } - //################ // STEP 12 # //################ diff --git a/src/northbridge/via/vx800/dram_init.h b/src/northbridge/via/vx800/dram_init.h index e7f5e72d50..50007c18a7 100644 --- a/src/northbridge/via/vx800/dram_init.h +++ b/src/northbridge/via/vx800/dram_init.h @@ -74,7 +74,6 @@ //#define DATAWIDTHX8 8 //#define DATAWIDTHX4 4 - #define SPD_MEMORY_TYPE 2 /*Memory type FPM,EDO,SDRAM,DDR,DDR2 */ #define SPD_SDRAM_ROW_ADDR 3 /*Number of row addresses on this assembly */ #define SPD_SDRAM_COL_ADDR 4 /*Number of column addresses on this assembly */ @@ -244,7 +243,6 @@ void DRAMBankInterleave(DRAM_SYS_ATTR * DramAttr); /*Step14 Sizing*/ void DRAMSizingMATypeM(DRAM_SYS_ATTR * DramAttr); - //final_setting.c /*Step15 DDR fresh counter setting*/ void DRAMRefreshCounter(DRAM_SYS_ATTR * DramAttr); @@ -253,7 +251,6 @@ void DRAMRefreshCounter(DRAM_SYS_ATTR * DramAttr); /*Step16 Final register setting for improve performance*/ void DRAMRegFinalValue(DRAM_SYS_ATTR * DramAttr); - /*set UMA*/ void SetUMARam(); diff --git a/src/northbridge/via/vx800/dram_util.c b/src/northbridge/via/vx800/dram_util.c index d09acdaf6f..35c471fc80 100644 --- a/src/northbridge/via/vx800/dram_util.c +++ b/src/northbridge/via/vx800/dram_util.c @@ -41,8 +41,8 @@ Reference : None void via_write_phys(volatile u32 addr, volatile u32 value) { volatile u32 *ptr; - ptr = (volatile u32 *) addr; - *ptr = (volatile u32) value; + ptr = (volatile u32 *)addr; + *ptr = (volatile u32)value; } /*=================================================================== @@ -59,12 +59,11 @@ u32 via_read_phys(volatile u32 addr) volatile u32 *ptr; volatile u32 y; // ptr = (volatile u32 *)addr; - y = *(volatile u32 *) addr; + y = *(volatile u32 *)addr; // return *ptr; return y; } - /*=================================================================== Function : DimmRead() Precondition : @@ -77,12 +76,11 @@ Reference : None u32 DimmRead(volatile u32 x) { // volatile u32 z; volatile u32 y; - y = *(volatile u32 *) x; + y = *(volatile u32 *)x; return y; } - /*=================================================================== Function : DramBaseTest() Precondition : this function used to verify memory @@ -116,8 +114,7 @@ BOOLEAN DramBaseTest(u32 BaseAdd, u32 Length, } //write each test unit the value with TEST_PATTERN - for (Address = BaseAdd; Address < BaseAdd + Length; - Address += TestSpan) { + for (Address = BaseAdd; Address < BaseAdd + Length; Address += TestSpan) { for (i = 0; i < TestCount; i++) via_write_phys(Address + i * 4, TEST_PATTERN); if (PrintFlag) { @@ -131,15 +128,12 @@ BOOLEAN DramBaseTest(u32 BaseAdd, u32 Length, //compare each test unit with the value of TEST_PATTERN //and write it with compliment of TEST_PATTERN - for (Address = BaseAdd; Address < BaseAdd + Length; - Address += TestSpan) { + for (Address = BaseAdd; Address < BaseAdd + Length; Address += TestSpan) { for (i = 0; i < TestCount; i++) { Data = via_read_phys(Address + i * 4); - via_write_phys(Address + i * 4, - (u32) (~TEST_PATTERN)); + via_write_phys(Address + i * 4, (u32) (~TEST_PATTERN)); if (Data != TEST_PATTERN) { - PRINT_DEBUG_MEM - ("TEST_PATTERN ERROR !!!!! "); + PRINT_DEBUG_MEM("TEST_PATTERN ERROR !!!!! "); Address2 = Address + i * 4; PRINT_DEBUG_MEM_HEX32(Address2); PRINT_DEBUG_MEM(" : "); @@ -157,16 +151,13 @@ BOOLEAN DramBaseTest(u32 BaseAdd, u32 Length, } } - //compare each test unit with the value of ~TEST_PATTERN - for (Address = BaseAdd; Address < BaseAdd + Length; - Address += TestSpan) { + for (Address = BaseAdd; Address < BaseAdd + Length; Address += TestSpan) { for (i = (u8) (TestCount); i > 0; i--) { Data = via_read_phys(Address + (i - 1) * 4); if (Data != ~TEST_PATTERN) { - PRINT_DEBUG_MEM - ("~TEST_PATTERN ERROR !!!!! "); + PRINT_DEBUG_MEM("~TEST_PATTERN ERROR !!!!! "); Address2 = Address + (i - 1) * 4; PRINT_DEBUG_MEM_HEX32(Address2); PRINT_DEBUG_MEM(" : "); @@ -219,7 +210,6 @@ void DumpRegisters(INTN DevNum, INTN FuncNum) return; } - /*=================================================================== Function : dumpnorth() Precondition : diff --git a/src/northbridge/via/vx800/drdy_bl.c b/src/northbridge/via/vx800/drdy_bl.c index b5a78f1a7d..627fb28552 100644 --- a/src/northbridge/via/vx800/drdy_bl.c +++ b/src/northbridge/via/vx800/drdy_bl.c @@ -102,7 +102,6 @@ #define Rx54L1T P6IF_Misc_RFASTH #define Rx55L1T P6IF_Misc2_RHTSEL - #define PH0_0_0_0 0x00 #define PH0_0_0_1 0x01 #define PH0_0_0_2 0x02 @@ -276,7 +275,6 @@ static const u8 PT894_128bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] = } }; - static const u8 PT894_64bit_DELAYMD0_RCONV0[6][6][PT894_RDRDY_TBL_Width] = // ----------------------------------------------------------------------------------------------------------------- // RX60 RX61 RX62 RX63 RX64 RX65 RX66 RX67 RX54[3,1] RX55[3,1] CPU/DRAM @@ -341,7 +339,6 @@ static const u8 PT894_64bit_DELAYMD0_RCONV0[6][6][PT894_RDRDY_TBL_Width] = } }; - static const u8 PT894_64bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] = // ----------------------------------------------------------------------------------------------------------------- // RX60 RX61 RX62 RX63 RX64 RX65 RX66 RX67 RX54[3,1] RX55[3,1] CPU/DRAM @@ -418,7 +415,7 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr) this function has 3 switchs, correspond to 3 level of Drdy setting. 0:Slowest, 1:Default, 2:Optimize you can only open one switch - */ + */ #if 1 //this is slowest // 0 -> Slowest //Write slowest value to register @@ -541,7 +538,6 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr) #endif } - /*This routine process the ability for North Bridge side burst functionality There are 3 variances that are valid: 1. DIMM BL=8, chipset BL=8 @@ -568,8 +564,9 @@ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr) for (Sockets = 0; Sockets < 2; Sockets++) { if (DramAttr->DimmInfo[Sockets].bPresence) { BL &= - (DramAttr->DimmInfo[Sockets]. - SPDDataBuf[SPD_SDRAM_BURSTLENGTH]); + (DramAttr-> + DimmInfo[Sockets].SPDDataBuf + [SPD_SDRAM_BURSTLENGTH]); } } @@ -585,8 +582,7 @@ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr) #if ENABLE_CHB if (DramAttr->RankNumChB > 0) { - BL = DramAttr->DimmInfo[2]. - SPDDataBuf[SPD_SDRAM_BURSTLENGTH]; + BL = DramAttr->DimmInfo[2].SPDDataBuf[SPD_SDRAM_BURSTLENGTH]; //Rx6c[1], CHB burst length if (BL & 0x08) /*CHB support BL=8 */ BL = 0x2; /*set bit1 */ diff --git a/src/northbridge/via/vx800/driving_clk_phase_data.h b/src/northbridge/via/vx800/driving_clk_phase_data.h index f6c8feace8..fd3751c44c 100644 --- a/src/northbridge/via/vx800/driving_clk_phase_data.h +++ b/src/northbridge/via/vx800/driving_clk_phase_data.h @@ -67,4 +67,4 @@ //extern u8 Fixed_DQSB_1_2_Rank_Table[4][2]; //extern u8 Fixed_DQSB_3_4_Rank_Table[4][2]; -#endif /* DRIVINGCLKPHASEDATA_H */ +#endif /* DRIVINGCLKPHASEDATA_H */ diff --git a/src/northbridge/via/vx800/driving_setting.c b/src/northbridge/via/vx800/driving_setting.c index 3bdfdf391f..c6a7edda05 100644 --- a/src/northbridge/via/vx800/driving_setting.c +++ b/src/northbridge/via/vx800/driving_setting.c @@ -55,7 +55,6 @@ void DRAMDriving(DRAM_SYS_ATTR * DramAttr) DrivingDCLK(DramAttr); } - /* ODT Control for DQ/DQS/CKE/SCMD/DCLKO in ChA & ChB which include driving enable/range and strong/weak selection @@ -158,7 +157,6 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr) Data |= 0; pci_write_config8(MEMCTRL, 0x9e, Data); - if (DIMMFREQ_400 == DramAttr->DramFreq) Data = 0x0; else if (DIMMFREQ_533 == DramAttr->DramFreq) @@ -171,7 +169,6 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr) Data = 0; pci_write_config8(MEMCTRL, 0x9f, Data); - /*channel A ODT select */ if (DramAttr->DimmNumChA > 0) { Data = pci_read_config8(MEMCTRL, 0xd5); @@ -190,7 +187,6 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr) Data |= 0x00; /*if rank number is 1or2, clear bit7 */ pci_write_config8(MEMCTRL, 0xd7, Data); - /*channel A */ Data = pci_read_config8(MEMCTRL, 0xd5); Data &= 0xF3; //bit2,3 @@ -212,12 +208,10 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr) } if (!bFound) { /*set default value */ Data = - ODTLookup_TBL[ODTLookup_Tbl_count - - 1][1]; + ODTLookup_TBL[ODTLookup_Tbl_count - 1][1]; } pci_write_config8(MEMCTRL, 0x9c, Data); - //set CHA MD ODT control State Dynamic-on Data = pci_read_config8(MEMCTRL, 0xD4); Data &= 0xC9; @@ -252,7 +246,6 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr) Data |= 0x00; /*if rank number is 1or2, clear bit7 */ pci_write_config8(MEMCTRL, 0xd7, Data); - Data = pci_read_config8(MEMCTRL, 0xd5); Data &= 0xFC; if (DramAttr->DimmNumChB == 2) /*2 Dimm, 3or4 Ranks */ @@ -267,7 +260,6 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr) Data |= 0x08; pci_write_config8(MEMCTRL, 0xD4, Data); - //enable CHB differential DQS input Data = pci_read_config8(MEMCTRL, 0x9E); Data |= 0x02; diff --git a/src/northbridge/via/vx800/final_setting.c b/src/northbridge/via/vx800/final_setting.c index 165c887d8a..97cc21820a 100644 --- a/src/northbridge/via/vx800/final_setting.c +++ b/src/northbridge/via/vx800/final_setting.c @@ -51,8 +51,7 @@ void DRAMRefreshCounter(DRAM_SYS_ATTR * DramAttr) Dram_256_Mb = 0; for (i = 0; i < MAX_SOCKETS; i++) { - if (DramAttr->DimmInfo[i].SPDDataBuf[SPD_SDRAM_ROW_ADDR] == - 13) { + if (DramAttr->DimmInfo[i].SPDDataBuf[SPD_SDRAM_ROW_ADDR] == 13) { Dram_256_Mb = 1; break; } @@ -63,7 +62,6 @@ void DRAMRefreshCounter(DRAM_SYS_ATTR * DramAttr) pci_write_config8(MEMCTRL, 0x6a, Data); } - /*=================================================================== Function : DRAMRegFinalValue() Precondition : diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c index ed4184ec77..b81b90de79 100644 --- a/src/northbridge/via/vx800/freq_setting.c +++ b/src/northbridge/via/vx800/freq_setting.c @@ -99,7 +99,6 @@ void DRAMFreqSetting(DRAM_SYS_ATTR * DramAttr) } - /* calculate CL and dram freq DDR1 @@ -134,13 +133,13 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) for (SckId = 0; SckId < MAX_SOCKETS; SckId++) { if (DramAttr->DimmInfo[SckId].bPresence) { /*all DIMM supported CL */ AllDimmSupportedCL &= - (DramAttr->DimmInfo[SckId]. - SPDDataBuf[SPD_SDRAM_CAS_LATENCY]); + (DramAttr-> + DimmInfo[SckId].SPDDataBuf[SPD_SDRAM_CAS_LATENCY]); } } if (!AllDimmSupportedCL) { /*if equal 0, no supported CL */ PRINT_DEBUG_MEM("SPD Data Error, Can not get CL !!!! \r"); - for (;;); + for (;;) ; } /*Get CL Value */ @@ -164,8 +163,8 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) for (SckId = 0; SckId < MAX_SOCKETS; SckId++) { if (DramAttr->DimmInfo[SckId].bPresence) { Tmp = - (DramAttr->DimmInfo[SckId]. - SPDDataBuf[SPD_SDRAM_CAS_LATENCY]); + (DramAttr-> + DimmInfo[SckId].SPDDataBuf[SPD_SDRAM_CAS_LATENCY]); tmpMask = 0x40; for (TmpId = 7; TmpId > 0; TmpId--) { if ((Tmp & tmpMask) == tmpMask) @@ -174,16 +173,19 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) } if (TmpId - BitId == 0) { /*get Cycle time for X, SPD BYTE9 */ TmpCycTime = - DramAttr->DimmInfo[SckId]. - SPDDataBuf[SPD_SDRAM_TCLK_X]; + DramAttr-> + DimmInfo[SckId].SPDDataBuf + [SPD_SDRAM_TCLK_X]; } else if (TmpId - BitId == 1) { /*get Cycle time for X-1, SPD BYTE23 */ TmpCycTime = - DramAttr->DimmInfo[SckId]. - SPDDataBuf[SPD_SDRAM_TCLK_X_1]; + DramAttr-> + DimmInfo[SckId].SPDDataBuf + [SPD_SDRAM_TCLK_X_1]; } else if (TmpId - BitId == 2) { /*get cycle time for X-2, SPD BYTE25 */ TmpCycTime = - DramAttr->DimmInfo[SckId]. - SPDDataBuf[SPD_SDRAM_TCLK_X_2]; + DramAttr-> + DimmInfo[SckId].SPDDataBuf + [SPD_SDRAM_TCLK_X_2]; } else { //error!!! } @@ -194,7 +196,7 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) if (CycTime <= 0) { //error! - for (;;); + for (;;) ; } /* cycle time value diff --git a/src/northbridge/via/vx800/northbridge.h b/src/northbridge/via/vx800/northbridge.h index 577efe6291..bcbeffb284 100644 --- a/src/northbridge/via/vx800/northbridge.h +++ b/src/northbridge/via/vx800/northbridge.h @@ -22,4 +22,4 @@ extern unsigned int vx800_scan_root_bus(device_t root, unsigned int max); -#endif /* NORTHBRIDGE_VIA_VX800_H */ +#endif /* NORTHBRIDGE_VIA_VX800_H */ diff --git a/src/northbridge/via/vx800/raminit.c b/src/northbridge/via/vx800/raminit.c index 8af9e74967..bf1eed92e9 100644 --- a/src/northbridge/via/vx800/raminit.c +++ b/src/northbridge/via/vx800/raminit.c @@ -24,7 +24,6 @@ #define DEBUG_RAM_SETUP 1 - #ifdef DEBUG_RAM_SETUP #define PRINT_DEBUG_MEM(x) print_debug(x) #define PRINT_DEBUG_MEM_HEX8(x) print_debug_hex8(x) diff --git a/src/northbridge/via/vx800/raminit.h b/src/northbridge/via/vx800/raminit.h index 7885aa7dd2..c813aba393 100644 --- a/src/northbridge/via/vx800/raminit.h +++ b/src/northbridge/via/vx800/raminit.h @@ -21,4 +21,4 @@ #define RAMINIT_H #define MEMCTRL PCI_DEV(0,0,3) -#endif /* RAMINIT_H */ +#endif /* RAMINIT_H */ diff --git a/src/northbridge/via/vx800/rank_map.c b/src/northbridge/via/vx800/rank_map.c index f86a3648d3..00e1e47fa3 100644 --- a/src/northbridge/via/vx800/rank_map.c +++ b/src/northbridge/via/vx800/rank_map.c @@ -23,7 +23,6 @@ extern void DRAMSetVRNum(DRAM_SYS_ATTR * DramAttr, extern void SetEndingAddr(DRAM_SYS_ATTR * DramAttr, u8 VirRank, // Ending address register number indicator (INDEX INT8 Value); // (value) add or subtract value to this and after banks - void DRAMClearEndingAddress(DRAM_SYS_ATTR * DramAttr); void DRAMSizingEachRank(DRAM_SYS_ATTR * DramAttr); @@ -57,8 +56,8 @@ void DRAMBankInterleave(DRAM_SYS_ATTR * DramAttr) if ((DramAttr->RankPresentMap & Shift) != 0) { CurrentDimminfo = &(DramAttr->DimmInfo[RankNO >> 1]); //this Rank in a dimm SpdBAData = - (u8) (CurrentDimminfo-> - SPDDataBuf[SPD_SDRAM_NO_OF_BANKS]); + (u8) (CurrentDimminfo->SPDDataBuf + [SPD_SDRAM_NO_OF_BANKS]); if (SpdBAData == 4) Count = 2; else if (SpdBAData == 8) @@ -76,12 +75,10 @@ void DRAMBankInterleave(DRAM_SYS_ATTR * DramAttr) Data |= (Bank << 6); pci_write_config8(MEMCTRL, 0x69, Data); - if (DramAttr->DimmNumChB > 0) { CurrentDimminfo = &(DramAttr->DimmInfo[3]); //this Rank in a dimm SpdBAData = - (u8) (CurrentDimminfo-> - SPDDataBuf[SPD_SDRAM_NO_OF_BANKS]); + (u8) (CurrentDimminfo->SPDDataBuf[SPD_SDRAM_NO_OF_BANKS]); if (SpdBAData == 4) Bank = 2; else if (SpdBAData == 2) @@ -147,12 +144,9 @@ void DRAMSizingEachRank(DRAM_SYS_ATTR * DramAttr) for (Slot = 0; Slot < 2; Slot++) { if (!DramAttr->DimmInfo[Slot].bPresence) continue; - Rows = - DramAttr->DimmInfo[Slot]. - SPDDataBuf[SPD_SDRAM_ROW_ADDR]; + Rows = DramAttr->DimmInfo[Slot].SPDDataBuf[SPD_SDRAM_ROW_ADDR]; Columns = - DramAttr->DimmInfo[Slot]. - SPDDataBuf[SPD_SDRAM_COL_ADDR]; + DramAttr->DimmInfo[Slot].SPDDataBuf[SPD_SDRAM_COL_ADDR]; Banks = DramAttr->DimmInfo[Slot].SPDDataBuf[SPD_SDRAM_NO_OF_BANKS]; //this is Bank number not Bank address bit if (Banks == 4) Banks = 2; @@ -164,8 +158,9 @@ void DRAMSizingEachRank(DRAM_SYS_ATTR * DramAttr) RankIndex = 2 * Slot; DramAttr->RankSize[RankIndex] = Size; //if this module have two ranks - if ((DramAttr->DimmInfo[Slot]. - SPDDataBuf[SPD_SDRAM_DIMM_RANKS] & 0x07) == 0x01) { + if ((DramAttr-> + DimmInfo[Slot].SPDDataBuf[SPD_SDRAM_DIMM_RANKS] & 0x07) == + 0x01) { RankIndex++; DramAttr->RankSize[RankIndex] = Size; } @@ -189,8 +184,7 @@ void DRAMSizingEachRank(DRAM_SYS_ATTR * DramAttr) pci_write_config8(MEMCTRL, 0x53, Data); } #if 1 - for (RankIndex = 0; DramAttr->RankSize[RankIndex] != 0; - RankIndex++) { + for (RankIndex = 0; DramAttr->RankSize[RankIndex] != 0; RankIndex++) { PRINT_DEBUG_MEM("Rank:"); PRINT_DEBUG_MEM_HEX8(RankIndex); PRINT_DEBUG_MEM(", Size:"); @@ -235,11 +229,13 @@ void DRAMSetRankMAType(DRAM_SYS_ATTR * DramAttr) if (DramAttr->DimmInfo[SlotNum].bPresence) { for (j = 0; MAMapTypeTbl[j] != 0; j += 3) { if ((1 << MAMapTypeTbl[j]) == - DramAttr->DimmInfo[SlotNum]. - SPDDataBuf[SPD_SDRAM_NO_OF_BANKS] + DramAttr-> + DimmInfo[SlotNum].SPDDataBuf + [SPD_SDRAM_NO_OF_BANKS] && MAMapTypeTbl[j + 1] == - DramAttr->DimmInfo[SlotNum]. - SPDDataBuf[SPD_SDRAM_COL_ADDR]) { + DramAttr-> + DimmInfo[SlotNum].SPDDataBuf + [SPD_SDRAM_COL_ADDR]) { break; } } @@ -286,11 +282,9 @@ void DRAMSetEndingAddress(DRAM_SYS_ATTR * DramAttr) End = End + Size; // calculate current ending address, add the current Size to ending Vrank = RankNO; // get virtual Rank Data = End; // set begin/End address register to correspondig virtual Rank # - pci_write_config8(MEMCTRL, 0x40 + Vrank, - Data); + pci_write_config8(MEMCTRL, 0x40 + Vrank, Data); Data = Start; - pci_write_config8(MEMCTRL, 0x48 + Vrank, - Data); + pci_write_config8(MEMCTRL, 0x48 + Vrank, Data); PRINT_DEBUG_MEM("Rank: "); PRINT_DEBUG_MEM_HEX8(Vrank); PRINT_DEBUG_MEM(", Start:"); diff --git a/src/northbridge/via/vx800/timing_setting.c b/src/northbridge/via/vx800/timing_setting.c index 5e1847800a..a1d8e74812 100644 --- a/src/northbridge/via/vx800/timing_setting.c +++ b/src/northbridge/via/vx800/timing_setting.c @@ -70,7 +70,6 @@ void DRAMTimingSetting(DRAM_SYS_ATTR * DramAttr) SetTrtp(DramAttr); } - /* Set DRAM Timing: CAS Latency for DDR1 D0F3RX62 bit[0:2] for CAS Latency; @@ -91,7 +90,6 @@ void SetCL(DRAM_SYS_ATTR * DramAttr) pci_write_config8(MEMCTRL, 0x62, Data); } - /* Minimum row precharge time, Trp for DDR1/DDR2 D0F3Rx64[3:2] for Trp 2T~5T @@ -105,15 +103,14 @@ void SetTrp(DRAM_SYS_ATTR * DramAttr) u16 Max, Tmp; u8 Socket; - /*get the max Trp value from SPD data SPD Byte27, Bit7:2->1ns~63ns, Bit1:0->0ns, 0.25ns, 0.50ns, 0.75ns */ Max = 0; for (Socket = 0; Socket < MAX_SOCKETS; Socket++) { if (DramAttr->DimmInfo[Socket].bPresence) { Tmp = - (u16) (DramAttr->DimmInfo[Socket]. - SPDDataBuf[SPD_SDRAM_TRP]); + (u16) (DramAttr-> + DimmInfo[Socket].SPDDataBuf[SPD_SDRAM_TRP]); if (Tmp > Max) Max = Tmp; } @@ -144,7 +141,6 @@ void SetTrp(DRAM_SYS_ATTR * DramAttr) pci_write_config8(MEMCTRL, 0x62, Data); } - /* Minimum RAS to CAS dely,Trcd for DDR1/DDR2 D0F3Rx64[7:6] for Trcd @@ -158,15 +154,14 @@ void SetTrcd(DRAM_SYS_ATTR * DramAttr) u16 Max, Tmp; u8 Socket; - /*get the max Trcd value from SPD data SPD Byte29, Bit7:2->1ns~63ns, Bit1:0->0ns, 0.25ns, 0.50ns, 0.75ns */ Max = 0; for (Socket = 0; Socket < MAX_SOCKETS; Socket++) { if (DramAttr->DimmInfo[Socket].bPresence) { Tmp = - (u16) (DramAttr->DimmInfo[Socket]. - SPDDataBuf[SPD_SDRAM_TRCD]); + (u16) (DramAttr-> + DimmInfo[Socket].SPDDataBuf[SPD_SDRAM_TRCD]); if (Tmp > Max) Max = Tmp; } @@ -204,24 +199,21 @@ void SetTras(DRAM_SYS_ATTR * DramAttr) u16 Max, Tmp; u8 Socket; - /*get the max Tras value from SPD data SPD byte30: bit0:7 1ns~255ns */ Max = 0; for (Socket = 0; Socket < MAX_SOCKETS; Socket++) { if (DramAttr->DimmInfo[Socket].bPresence) { Tmp = - (u16) (DramAttr->DimmInfo[Socket]. - SPDDataBuf[SPD_SDRAM_TRAS]); + (u16) (DramAttr-> + DimmInfo[Socket].SPDDataBuf[SPD_SDRAM_TRAS]); if (Tmp > Max) Max = Tmp; } } /*Calculate clock,value range 5T-20T */ - Tmp = - (u16) ((Max * 100 + DramAttr->DramCyc - - 1) / (DramAttr->DramCyc)); + Tmp = (u16) ((Max * 100 + DramAttr->DramCyc - 1) / (DramAttr->DramCyc)); PRINT_DEBUG_MEM("Tras ="); PRINT_DEBUG_MEM_HEX16(Tmp); PRINT_DEBUG_MEM("\r"); @@ -259,12 +251,13 @@ void SetTrfc(DRAM_SYS_ATTR * DramAttr) for (Socket = 0; Socket < MAX_SOCKETS; Socket++) { if (DramAttr->DimmInfo[Socket].bPresence) { Tmp = - (u32) (DramAttr->DimmInfo[Socket]. - SPDDataBuf[SPD_SDRAM_TRFC]) * 100; + (u32) (DramAttr-> + DimmInfo[Socket].SPDDataBuf[SPD_SDRAM_TRFC]) + * 100; /*only DDR2 need to add byte 40 bit[7:4] */ Byte40 = - (DramAttr->DimmInfo[Socket]. - SPDDataBuf[SPD_SDRAM_TRFC2]); + (DramAttr-> + DimmInfo[Socket].SPDDataBuf[SPD_SDRAM_TRFC2]); /*if bit0 = 1, byte42(RFC)+256ns, SPD spec JEDEC standard No.21.c */ if (Byte40 & 0x01) Tmp += (256 * 100); @@ -313,7 +306,6 @@ void SetTrfc(DRAM_SYS_ATTR * DramAttr) pci_write_config8(MEMCTRL, 0x61, Data); } - /* Minimum row active to row active delay: Trrd for DDR1/DDR2 D0F3Rx61[7:6]:Trrd 00->2T, 01->3T, 10->4T, 11->5T @@ -327,15 +319,14 @@ void SetTrrd(DRAM_SYS_ATTR * DramAttr) u16 Max, Tmp; u8 Socket; - /*get the max Trrd value from SPD data SPD Byte28, Bit7:2->1ns~63ns, Bit1:0->0ns, 0.25ns, 0.50ns, 0.75ns */ Max = 0; for (Socket = 0; Socket < MAX_SOCKETS; Socket++) { if (DramAttr->DimmInfo[Socket].bPresence) { Tmp = - (u16) (DramAttr->DimmInfo[Socket]. - SPDDataBuf[SPD_SDRAM_TRRD]); + (u16) (DramAttr-> + DimmInfo[Socket].SPDDataBuf[SPD_SDRAM_TRRD]); if (Tmp > Max) Max = Tmp; } @@ -361,7 +352,6 @@ void SetTrrd(DRAM_SYS_ATTR * DramAttr) pci_write_config8(MEMCTRL, 0x61, Data); } - /* Write recovery time: Twr for DDR1/DDR2 Device 0 Function 3:REG63[7:5]:Twr 00->2T 01->3T 10->4T 11->5T @@ -381,8 +371,8 @@ void SetTwr(DRAM_SYS_ATTR * DramAttr) for (Socket = 0; Socket < MAX_SOCKETS; Socket++) { if (DramAttr->DimmInfo[Socket].bPresence) { Tmp = - (u16) (DramAttr->DimmInfo[Socket]. - SPDDataBuf[SPD_SDRAM_TWR]); + (u16) (DramAttr-> + DimmInfo[Socket].SPDDataBuf[SPD_SDRAM_TWR]); if (Tmp > Max) Max = Tmp; } @@ -405,7 +395,6 @@ void SetTwr(DRAM_SYS_ATTR * DramAttr) pci_write_config8(MEMCTRL, 0x63, Data); } - /* Internal write to read command delay: Twtr for DDR1/DDR2 Device 0 Function 3:REG63[1,0]:Twtr DDR: 1T or 2T; DDR2 2T or 3T @@ -425,8 +414,8 @@ void SetTwtr(DRAM_SYS_ATTR * DramAttr) for (Socket = 0; Socket < MAX_SOCKETS; Socket++) { if (DramAttr->DimmInfo[Socket].bPresence) { Tmp = - (u16) (DramAttr->DimmInfo[Socket]. - SPDDataBuf[SPD_SDRAM_TWTR]); + (u16) (DramAttr-> + DimmInfo[Socket].SPDDataBuf[SPD_SDRAM_TWTR]); if (Tmp > Max) Max = Tmp; } @@ -448,7 +437,6 @@ void SetTwtr(DRAM_SYS_ATTR * DramAttr) pci_write_config8(MEMCTRL, 0x63, Data); } - /* Internal read to precharge command delay, Trtp for DDR1/DDR2 Device 0 Function 3:REG63[3]:Trtp 2T or 3T @@ -462,15 +450,14 @@ void SetTrtp(DRAM_SYS_ATTR * DramAttr) u16 Max, Tmp; u8 Socket; - /*get the max Trtp value from SPD data SPD Byte38, Bit7:2->1ns~63ns, Bit1:0->0ns, 0.25ns, 0.50ns, 0.75ns */ Max = 0; for (Socket = 0; Socket < MAX_SOCKETS; Socket++) { if (DramAttr->DimmInfo[Socket].bPresence) { Tmp = - (u16) (DramAttr->DimmInfo[Socket]. - SPDDataBuf[SPD_SDRAM_TRTP]); + (u16) (DramAttr-> + DimmInfo[Socket].SPDDataBuf[SPD_SDRAM_TRTP]); if (Tmp > Max) Max = Tmp; } diff --git a/src/northbridge/via/vx800/translator_ddr2_init.c b/src/northbridge/via/vx800/translator_ddr2_init.c index cb54aba1af..362742ec91 100644 --- a/src/northbridge/via/vx800/translator_ddr2_init.c +++ b/src/northbridge/via/vx800/translator_ddr2_init.c @@ -24,7 +24,6 @@ #define TRUE 1 #define FALSE 0 - typedef int8_t INT8; typedef unsigned long uintn_t; typedef uintn_t UINTN; diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c index f8aaf74eef..e670a940ec 100644 --- a/src/northbridge/via/vx800/uma_ram_setting.c +++ b/src/northbridge/via/vx800/uma_ram_setting.c @@ -32,7 +32,6 @@ typedef struct __UMA_RAM_tag { #define UMARAM_8M 1 #define UMARAM_0M 0 - #define FB_512M 0 #define FB_256M 0x40 #define FB_128M 0x60 @@ -77,7 +76,6 @@ void SetUMARam(void) SLD1F0Val = 0; VgaPortVal = 0; - ByteVal = pci_read_config8(MEMCTRL, 0xa1); ByteVal |= 0x80; pci_write_config8(MEMCTRL, 0xa1, ByteVal); @@ -134,7 +132,6 @@ void SetUMARam(void) ByteVal = (ByteVal & 0x8f) | (SLD0F3Val << 4); pci_write_config8(MEMCTRL, 0xa1, ByteVal); - // vga_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VGA, 0); //RxB2 may be for S.L. and RxB1 may be for L. L. @@ -142,7 +139,6 @@ void SetUMARam(void) ByteVal = SLD1F0Val; pci_write_config8(vga_dev, 0xb2, ByteVal); - //set M1 size //ByteVal=pci_read_config8(MEMCTRL, 0xa3); //ByteVal = 0x02; @@ -150,16 +146,10 @@ void SetUMARam(void) PRINT_DEBUG_MEM("UMA setting - 3\n"); - - - //Enable p2p IO/mem ByteVal = 0x07; pci_write_config8(vga_dev, 0x04, ByteVal); - - - //must set SL and MMIO base, or else when enable GFX memory space, system will hang //set S.L base Tmp = pci_read_config32(vga_dev, 0x10); @@ -177,27 +167,23 @@ void SetUMARam(void) Tmp = VIACONFIG_VGA_PCI_14; pci_write_config32(vga_dev, 0x14, Tmp); - //enable direct cpu frame buffer access i = pci_rawread_config8(PCI_RAWDEV(0, 0, 3), 0xa1); i = (i & 0xf0) | (VIACONFIG_VGA_PCI_10 >> 28); pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa1, i); pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa0, 0x01); - //enable GFx memory space access control for S.L and mmio ByteVal = pci_read_config8(d0f0_dev, 0xD4); ByteVal |= 0x03; //ByteVal |= 0x01; pci_write_config8(d0f0_dev, 0xD4, ByteVal); - //enable Base VGA 16 Bits Decode ByteVal = pci_read_config8(d0f0_dev, 0xfe); ByteVal |= 0x10; pci_write_config8(d0f0_dev, 0xfe, ByteVal); - //disable CHB L.L //set VGA memory selection ByteVal = pci_read_config8(vga_dev, 0xb0); @@ -233,7 +219,6 @@ void SetUMARam(void) // ByteVal |= 0x01; // outb(ByteVal,0x03C2); - #if 1 //bios porting guide has no this two defination: 3d on 3d4/3d5 and 39 on 3c4/3c5 //set frequence 0x3D5.3d[7:4] outb(0x3d, 0x03d4); @@ -304,7 +289,6 @@ void SetUMARam(void) //calculate SL Base Address SLBase = (RamSize << 26) - (UmaSize << 20); - outb(0x6D, 0x03c4); //SL Base[28:21] outb((u8) ((SLBase >> 21) & 0xFF), 0x03c5); @@ -339,7 +323,6 @@ void SetUMARam(void) ByteVal = (ByteVal & 0xE5) | 0x1A; outb(ByteVal, 0x03c5); - outb(0xf3, 0x03d4); ByteVal = inb(0x03d5); ByteVal = (ByteVal & 0xE5) | 0x1A; @@ -381,7 +364,6 @@ void SetUMARam(void) 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, }; - u8 table3c0space[0xc0] = { 0x11, 0x00, 0x10, 0x01, 0x26, 0x3D, 0xFF, 0x00, 0x10, 0x3F, 0x00, 0x00, 0x2F, 0x00, 0x22, 0x00, @@ -415,7 +397,6 @@ void SetUMARam(void) outb(table3c0space[i], 0x03c0 + i); } - for (i = 0; i < 0x70; i++) { outb(i, 0x03c4); outb(table3c43c5[i], 0x03c5); diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index 03680786e5..b29f12ae49 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -84,7 +84,6 @@ static void vga_init(device_t dev) //*/ printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__); - #if 1 printk_debug("INSTALL REAL-MODE IDT\n"); setup_realmode_idt(); @@ -126,12 +125,11 @@ static void vga_init(device_t dev) static void vga_read_resources(device_t dev) { - dev->rom_address = (void *) (0xffffffff - FULL_ROM_SIZE + 1); + dev->rom_address = (void *)(0xffffffff - FULL_ROM_SIZE + 1); dev->on_mainboard = 1; pci_dev_read_resources(dev); } - static struct device_operations vga_operations = { .read_resources = vga_read_resources, .set_resources = pci_dev_set_resources, @@ -140,7 +138,6 @@ static struct device_operations vga_operations = { .ops_pci = 0, }; - static const struct pci_driver vga_driver __pci_driver = { .ops = &vga_operations, .vendor = PCI_VENDOR_ID_VIA, diff --git a/src/northbridge/via/vx800/vgabios.c b/src/northbridge/via/vx800/vgabios.c index 6155a79581..34d3bce939 100644 --- a/src/northbridge/via/vx800/vgabios.c +++ b/src/northbridge/via/vx800/vgabios.c @@ -7,7 +7,6 @@ #include <string.h> #include "vgachip.h" - /* vgabios.c. Derived from: */ /*------------------------------------------------------------ -*- C -*- @@ -306,7 +305,7 @@ void do_vgabios(void) /* clear vga bios data area */ for (i = 0x400; i < 0x500; i++) { - *(unsigned char *) i = 0; + *(unsigned char *)i = 0; } dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0); @@ -315,8 +314,7 @@ void do_vgabios(void) printk_debug("NO VGA FOUND\n"); return; } - printk_debug("found VGA: vid=%x, did=%x\n", dev->vendor, - dev->device); + printk_debug("found VGA: vid=%x, did=%x\n", dev->vendor, dev->device); /* declare rom address here - keep any config data out of the way * of core LXB stuff */ @@ -324,28 +322,25 @@ void do_vgabios(void) rom = 0xffffffff - FULL_ROM_SIZE + 1; pci_write_config32(dev, PCI_ROM_ADDRESS, rom | 1); printk_debug("rom base: %x\n", rom); - buf = (unsigned char *) rom; + buf = (unsigned char *)rom; printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__); if ((buf[0] == 0x55) && (buf[1] == 0xaa)) { - memcpy((void *) 0xc0000, buf, size); - + memcpy((void *)0xc0000, buf, size); printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__); write_protect_vgabios(); // in northbridge // check signature again - buf = (unsigned char *) 0xc0000; + buf = (unsigned char *)0xc0000; if (buf[0] == 0x55 && buf[1] == 0xAA) { busdevfn = - (dev->bus->secondary << 8) | dev->path.pci. - devfn; + (dev->bus->secondary << 8) | dev->path.pci.devfn; printk_debug("bus/devfn = %#x\n", busdevfn); real_mode_switch_call_vga(busdevfn); } else - printk_debug - ("Failed to copy VGA BIOS to 0xc0000\n"); + printk_debug("Failed to copy VGA BIOS to 0xc0000\n"); } else printk_debug("BAD SIGNATURE 0x%x 0x%x\n", buf[0], buf[1]); @@ -354,7 +349,6 @@ void do_vgabios(void) pci_write_config32(dev, PCI_ROM_ADDRESS, 0); } - // we had hoped to avoid this. // this is a stub IDT only. It's main purpose is to ignore calls // to the BIOS. @@ -399,8 +393,7 @@ void debughandler(void) " loop dbh1 \n" " popw %cx \n" " iret \n" - "end_debughandle: \n" - ".code32 \n"); + "end_debughandle: \n" ".code32 \n"); } // Calling conventions. The first C function is called with this stuff @@ -492,8 +485,7 @@ enum { int pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, - unsigned long *pecx, unsigned long *peax, - unsigned long *pflags); + unsigned long *pecx, unsigned long *peax, unsigned long *pflags); int handleint21(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, unsigned long *pesp, @@ -536,8 +528,7 @@ int biosint(unsigned long intnumber, if (esp < 0x1000) { printk_debug("Stack contents: "); while (esp < 0x1000) { - printk_debug("0x%04x ", - *(unsigned short *) esp); + printk_debug("0x%04x ", *(unsigned short *)esp); esp += 2; } printk_debug("\n"); @@ -573,14 +564,13 @@ int biosint(unsigned long intnumber, return ret; } - void setup_realmode_idt(void) { extern unsigned char idthandle, end_idthandle; extern unsigned char debughandle, end_debughandle; int i; - struct realidt *idts = (struct realidt *) 0; + struct realidt *idts = (struct realidt *)0; int codesize = &end_idthandle - &idthandle; unsigned char *intbyte, *codeptr; @@ -595,8 +585,8 @@ void setup_realmode_idt(void) // and get it that way. But that's really disgusting. for (i = 0; i < 256; i++) { idts[i].cs = 0; - codeptr = (char *) 4096 + i * codesize; - idts[i].offset = (unsigned) codeptr; + codeptr = (char *)4096 + i * codesize; + idts[i].offset = (unsigned)codeptr; memcpy(codeptr, &idthandle, codesize); intbyte = codeptr + 3; *intbyte = i; @@ -608,7 +598,7 @@ void setup_realmode_idt(void) // int10. // calling convention here is the same as INTs, we can reuse // the int entry code. - codeptr = (char *) 0xff065; + codeptr = (char *)0xff065; memcpy(codeptr, &idthandle, codesize); intbyte = codeptr + 3; *intbyte = 0x42; /* int42 is the relocated int10 */ @@ -617,7 +607,7 @@ void setup_realmode_idt(void) VBIOS will call f000:f859 instead of sending int15. calling convertion here is the same as INTs, we can reuse the int entry code. */ - codeptr = (char *) 0xff859; + codeptr = (char *)0xff859; memcpy(codeptr, &idthandle, codesize); intbyte = codeptr + 3; *intbyte = 0x15; @@ -628,11 +618,8 @@ void setup_realmode_idt(void) idts[1].offset = 16384; memcpy(16384, &debughandle, &end_debughandle - &debughandle); - } - - enum { CHECK = 0xb001, FINDDEV = 0xb102, @@ -665,7 +652,7 @@ pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, unsigned long ecx = *pecx; unsigned long eax = *peax; unsigned long flags = *pflags; - unsigned short func = (unsigned short) eax; + unsigned short func = (unsigned short)eax; int retval = 0; unsigned short devid, vendorid, devfn; short devindex; /* Use short to get rid of garbage in upper half of 32-bit register */ @@ -684,8 +671,7 @@ pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, vendorid = *pedx; devindex = *pesi; dev = 0; - while ((dev = - dev_find_device(vendorid, devid, dev))) { + while ((dev = dev_find_device(vendorid, devid, dev))) { if (devindex <= 0) break; devindex--; @@ -775,7 +761,6 @@ pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, return retval; } - /* return value of int0x15(int21) AH AL Completion status ?? 5Fh Function call supported @@ -785,8 +770,7 @@ AH AL Completion status */ int handleint21(unsigned long *edi, unsigned long *esi, unsigned long *ebp, unsigned long *esp, unsigned long *ebx, unsigned long *edx, - unsigned long *ecx, unsigned long *eax, - unsigned long *flags) + unsigned long *ecx, unsigned long *eax, unsigned long *flags) { int res = -1; switch (*eax & 0xffff) { diff --git a/src/northbridge/via/vx800/vgachip.h b/src/northbridge/via/vx800/vgachip.h index 86e948bd91..1e17d90f66 100644 --- a/src/northbridge/via/vx800/vgachip.h +++ b/src/northbridge/via/vx800/vgachip.h @@ -31,4 +31,4 @@ void do_vgabios(void); void setup_realmode_idt(void); void write_protect_vgabios(void); -#endif /* _PC80_VGABIOS */ +#endif /* _PC80_VGABIOS */ diff --git a/src/northbridge/via/vx800/vx800.h b/src/northbridge/via/vx800/vx800.h index 3955f1fc4c..f77fd95b19 100644 --- a/src/northbridge/via/vx800/vx800.h +++ b/src/northbridge/via/vx800/vx800.h @@ -20,13 +20,14 @@ #ifndef VX800_H #define VX800_H 1 - #ifndef __ROMCC__ -static void vx800_noop(){} +static void vx800_noop() +{ +} #endif #define REV_B0 0x10 #define REV_B1 0x11 -#define REV_B2 0x12 +#define REV_B2 0x12 #define REV_B3 0x13 #define REV_B4 0x14 #define REV_B2 0xB4 @@ -63,9 +64,6 @@ static void vx800_noop(){} #define RAM_COMMAND_MRS 0x3 #define RAM_COMMAND_CBR 0x4 - - - /* IDE specific bits */ #define IDE_MODE_REG 0x09 #define IDE0_NATIVE_MODE (1 << 0) @@ -77,7 +75,6 @@ static void vx800_noop(){} #define IDE1_DATA_ADDR 0x170 #define IDE1_CONTROL_ADDR 0x370 - /* By Award default, Via default is 0xCC0 */ #define BUS_MASTER_ADDR 0xfe00 @@ -85,14 +82,11 @@ static void vx800_noop(){} #define ENABLE_IDE0 (1 << 0) #define ENABLE_IDE1 (1 << 1) - - #define VX800_ACPI_IO_BASE 0x0400 - #define NB_APIC_REG 0,0,5, -#define NB_PXPTRF_REG NB_APIC_REG -#define NB_MSGC_REG NB_APIC_REG +#define NB_PXPTRF_REG NB_APIC_REG +#define NB_MSGC_REG NB_APIC_REG #define NB_HOST_REG 0,0,2, #define NB_P6IF_REG NB_HOST_REG @@ -103,7 +97,6 @@ static void vx800_noop(){} #define NB_D3F0_REG 0,3, 0, #define NB_D3F1_REG 0,3, 1, - #define SB_LPC_REG 0,0x11,0, #define SB_VLINK_REG 0,0x11,7, #define SB_SATA_REG 0,0xf, 0, @@ -114,7 +107,6 @@ static void vx800_noop(){} #define SB_USB2_REG 0,0x10, 2, #define SB_EHCI_REG 0,0x10, 4, - #define VX800SB_APIC_ID 0x4 #define VX800SB_APIC_BASE 0xfec00000ULL #define VX800SB_APIC_DATA_OFFSET 0x10 diff --git a/src/northbridge/via/vx800/vx800_early_serial.c b/src/northbridge/via/vx800/vx800_early_serial.c index dfc5c3e235..6462a2d295 100644 --- a/src/northbridge/via/vx800/vx800_early_serial.c +++ b/src/northbridge/via/vx800/vx800_early_serial.c @@ -27,48 +27,46 @@ #define SIO_BASE 0x3f0 #define SIO_DATA SIO_BASE+1 -static void vx800_writesuper(uint8_t reg, uint8_t val) +static void vx800_writesuper(uint8_t reg, uint8_t val) { outb(reg, SIO_BASE); outb(val, SIO_DATA); } -static void vx800_writepnpaddr(uint8_t val) +static void vx800_writepnpaddr(uint8_t val) { outb(val, 0x2e); outb(val, 0xeb); } -static void vx800_writepnpdata(uint8_t val) +static void vx800_writepnpdata(uint8_t val) { outb(val, 0x2f); outb(val, 0xeb); } -static void vx800_writesiobyte(uint16_t reg, uint8_t val) +static void vx800_writesiobyte(uint16_t reg, uint8_t val) { outb(val, reg); } -static void vx800_writesioword(uint16_t reg, uint16_t val) +static void vx800_writesioword(uint16_t reg, uint16_t val) { outw(val, reg); } - /* regs we use: 85, and the southbridge devfn is defined by the mainboard */ -static void enable_vx800_serial(void) +static void enable_vx800_serial(void) { outb(6, 0x80); outb(0x03, 0x22); - //pci_write_config8(PCI_DEV(0,17,0),0xb4,0x7e); //pci_write_config8(PCI_DEV(0,17,0),0xb0,0x10); - + // turn on pnp vx800_writepnpaddr(0x87); vx800_writepnpaddr(0x87); @@ -96,7 +94,7 @@ static void enable_vx800_serial(void) // Set 115 kb vx800_writesioword(0x3f8, 1); // Set 9.6 kb - // WRITESIOWORD(0x3f8, 12) + // WRITESIOWORD(0x3f8, 12) // now set no parity, one stop, 8 bits vx800_writesiobyte(0x3fb, 3); // now turn on RTS, DRT @@ -107,4 +105,3 @@ static void enable_vx800_serial(void) vx800_writesiobyte(0x3f8, 48); outb(7, 0x80); } - diff --git a/src/northbridge/via/vx800/vx800_early_smbus.c b/src/northbridge/via/vx800/vx800_early_smbus.c index 03deedc8aa..247eab91fd 100644 --- a/src/northbridge/via/vx800/vx800_early_smbus.c +++ b/src/northbridge/via/vx800/vx800_early_smbus.c @@ -17,10 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include <device/pci_ids.h> - #include "vx800.h" -#define SMBUS_IO_BASE 0x0500 //from award bios -#define PMIO_BASE VX800_ACPI_IO_BASE //might as well set this while we're here +#include <device/pci_ids.h> +#include "vx800.h" +#define SMBUS_IO_BASE 0x0500 //from award bios +#define PMIO_BASE VX800_ACPI_IO_BASE //might as well set this while we're here #define SMBHSTSTAT SMBUS_IO_BASE + 0x0 #define SMBSLVSTAT SMBUS_IO_BASE + 0x1 @@ -64,10 +64,11 @@ /* Internal functions */ static void smbus_print_error(unsigned char host_status_register, int loops) { -// print_err("some i2c error\r\n"); +// print_err("some i2c error\r\n"); /* Check if there actually was an error */ - if ( host_status_register == 0x00 || host_status_register == 0x40 || - host_status_register == 0x42) return; + if (host_status_register == 0x00 || host_status_register == 0x40 || + host_status_register == 0x42) + return; print_err("smbus_error: "); print_err_hex8(host_status_register); print_err("\r\n"); @@ -98,7 +99,7 @@ static void smbus_wait_until_ready(void) loops = 0; /* Yes, this is a mess, but it's the easiest way to do it */ - while(((inb(SMBHSTSTAT) & 1) == 1) && (loops <= SMBUS_TIMEOUT)) { + while (((inb(SMBHSTSTAT) & 1) == 1) && (loops <= SMBUS_TIMEOUT)) { SMBUS_DELAY(); ++loops; } @@ -124,37 +125,37 @@ static unsigned int set_ics_data(unsigned char dev, int data, char len) inb(SMBHSTCTL); /* fill blocktransfer array */ - if (dev=0xd2) { + if (dev = 0xd2) { //char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b}; - outb(0x0d,SMBBLKDAT); - outb(0x00,SMBBLKDAT); - outb(0x3f,SMBBLKDAT); - outb(0xcd,SMBBLKDAT); - outb(0x7f,SMBBLKDAT); - outb(0xbf,SMBBLKDAT); - outb(0x1a,SMBBLKDAT); - outb(0x2a,SMBBLKDAT); - outb(0x01,SMBBLKDAT); - outb(0x0f,SMBBLKDAT); - outb(0x0b,SMBBLKDAT); - outb(0x80,SMBBLKDAT); - outb(0x8d,SMBBLKDAT); - outb(0x9b,SMBBLKDAT); + outb(0x0d, SMBBLKDAT); + outb(0x00, SMBBLKDAT); + outb(0x3f, SMBBLKDAT); + outb(0xcd, SMBBLKDAT); + outb(0x7f, SMBBLKDAT); + outb(0xbf, SMBBLKDAT); + outb(0x1a, SMBBLKDAT); + outb(0x2a, SMBBLKDAT); + outb(0x01, SMBBLKDAT); + outb(0x0f, SMBBLKDAT); + outb(0x0b, SMBBLKDAT); + outb(0x80, SMBBLKDAT); + outb(0x8d, SMBBLKDAT); + outb(0x9b, SMBBLKDAT); } else { //char d4_data[] = {0x08,0xff,0x3f,0x00,0x00,0xff,0xff,0xff,0xff}; - outb(0x08,SMBBLKDAT); - outb(0xff,SMBBLKDAT); - outb(0x3f,SMBBLKDAT); - outb(0x00,SMBBLKDAT); - outb(0x00,SMBBLKDAT); - outb(0xff,SMBBLKDAT); - outb(0xff,SMBBLKDAT); - outb(0xff,SMBBLKDAT); - outb(0xff,SMBBLKDAT); + outb(0x08, SMBBLKDAT); + outb(0xff, SMBBLKDAT); + outb(0x3f, SMBBLKDAT); + outb(0x00, SMBBLKDAT); + outb(0x00, SMBBLKDAT); + outb(0xff, SMBBLKDAT); + outb(0xff, SMBBLKDAT); + outb(0xff, SMBBLKDAT); + outb(0xff, SMBBLKDAT); } //for (i=0; i < len; i++) - // outb(data[i],SMBBLKDAT); + // outb(data[i],SMBBLKDAT); outb(dev, SMBXMITADD); outb(0, SMBHSTCMD); @@ -184,7 +185,7 @@ static unsigned int get_spd_data(unsigned int dimm, unsigned int offset) dimm &= 0x0E; dimm |= 0xA0; - outb(dimm|0x1, SMBXMITADD); + outb(dimm | 0x1, SMBXMITADD); outb(offset, SMBHSTCMD); outb(0x48, SMBHSTCTL); @@ -201,9 +202,12 @@ static void enable_smbus(void) { device_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), 0); + dev = + pci_locate_device(PCI_ID + (PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), + 0); - if (dev == PCI_DEV_INVALID) { + if (dev == PCI_DEV_INVALID) { /* This won't display text if enable_smbus() is before serial init */ die("Power Managment Controller not found\r\n"); } @@ -217,21 +221,21 @@ static void enable_smbus(void) /* Set to Award value */ pci_write_config8(dev, 0xd2, 0x05); - /* Make it work for I/O ...*/ + /* Make it work for I/O ... */ pci_write_config16(dev, 0x04, 0x0003); - /* - coreboot hangs at this two lines after os reboot(this even happen after I change os - reboot to cold reboot, this also interfere S3 wakeup)*/ + /* + coreboot hangs at this two lines after os reboot(this even happen after I change os + reboot to cold reboot, this also interfere S3 wakeup) */ /* Setup clock chips */ //set_ics_data(0xd2, 0, 14); //set_ics_data(0xd4, 0, 9); - + smbus_reset(); /* clear host data port */ outb(0x00, SMBHSTDAT0); SMBUS_DELAY(); - smbus_wait_until_ready(); + smbus_wait_until_ready(); } /** @@ -266,13 +270,15 @@ void smbus_fixup(const struct mem_controller *ctrl) * VT8237R has only been seen on DDR and DDR2 based systems, so far. */ for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) || - (result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++) { + (result > + SPD_MEMORY_TYPE_SDRAM_DDR3))); + i++) { if (current_slot > ram_slots) current_slot = 0; result = get_spd_data(ctrl->channel0[current_slot], - SPD_MEMORY_TYPE); + SPD_MEMORY_TYPE); current_slot++; PRINT_DEBUG("."); } @@ -290,24 +296,21 @@ static void dump_spd_data(void) int dimm, offset, regs; unsigned int val; - for(dimm = 0; dimm < 8; dimm++) - { + for (dimm = 0; dimm < 8; dimm++) { print_debug("SPD Data for DIMM "); print_debug_hex8(dimm); print_debug("\r\n"); val = get_spd_data(dimm, 0); - if(val == 0xff) - { + if (val == 0xff) { regs = 256; - } else if(val == 0x80) { + } else if (val == 0x80) { regs = 128; } else { print_debug("No DIMM present\r\n"); regs = 0; } - for(offset = 0; offset < regs; offset++) - { + for (offset = 0; offset < regs; offset++) { print_debug(" Offset "); print_debug_hex8(offset); print_debug(" = 0x"); diff --git a/src/northbridge/via/vx800/vx800_ide.c b/src/northbridge/via/vx800/vx800_ide.c index 4f9f8f9c49..f53f4ab551 100644 --- a/src/northbridge/via/vx800/vx800_ide.c +++ b/src/northbridge/via/vx800/vx800_ide.c @@ -27,75 +27,141 @@ #include "vx800.h" static const idedevicepcitable[16 * 12] = { -// -/*0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0xA8, 0xA8, 0xF0, 0x00, 0x00, 0xB6, -0x00, 0x00, 0x01, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, -0x00, 0xC2, 0xF9, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -*/ -// - 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0x99, 0x20, 0xf0, 0x00, 0x00, 0x20, - 0x00, 0x00, 0x17, 0xF1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, - 0x00, 0xc2, 0x09, 0x01, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -//legacybios xp pci value -/*0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x20, 0x00, 0x00, 0x00, 0xb6, -0x00, 0x00, 0x16, 0xF1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, -0x00, 0x02, 0x09, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -*/ -//rom legacybios on cn_8562b -/* -0x03, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0x99, 0x20, 0x60, 0x00, 0x00, 0x20, -0x00, 0x00, 0x1E, 0xF1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, -0x00, 0x02, 0x09, 0x01, 0x18, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -*/ -//from egacybios on c7_8562b -/*0x03, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0x5E, 0x20, 0x60, 0x00, 0x00, 0xB6, -0x00, 0x00, 0x1E, 0xF1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, -0x00, 0x02, 0x09, 0x01, 0x18, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, */ + /* + 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, + 0x00, 0x00, 0xA8, 0xA8, 0xF0, 0x00, 0x00, 0xB6, + 0x00, 0x00, 0x01, 0x21, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, + 0x00, 0xC2, 0xF9, 0x01, 0x10, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + */ + + 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, + 0x00, 0x00, 0x99, 0x20, 0xf0, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x17, 0xF1, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, + 0x00, 0xc2, 0x09, 0x01, 0x10, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + /* Legacy BIOS XP PCI value */ + /* + 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, + 0x00, 0x00, 0xa8, 0x20, 0x00, 0x00, 0x00, 0xb6, + 0x00, 0x00, 0x16, 0xF1, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, + 0x00, 0x02, 0x09, 0x00, 0x18, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + */ + + /* ROM legacy BIOS on cn_8562b */ + /* + 0x03, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, + 0x00, 0x00, 0x99, 0x20, 0x60, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x1E, 0xF1, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, + 0x00, 0x02, 0x09, 0x01, 0x18, 0x0C, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + */ + + /* From legacy BIOS on c7_8562b */ + /* + 0x03, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, + 0x00, 0x00, 0x5E, 0x20, 0x60, 0x00, 0x00, 0xB6, + 0x00, 0x00, 0x1E, 0xF1, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x09, 0xC4, 0x06, 0x11, 0x09, 0xC4, + 0x00, 0x02, 0x09, 0x01, 0x18, 0x0C, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x01, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + */ }; static void ide_init(struct device *dev) @@ -129,10 +195,8 @@ static void ide_init(struct device *dev) pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); #if 0 - - struct southbridge_via_vt8237r_config *sb = - (struct southbridge_via_vt8237r_config *) dev->chip_info; + (struct southbridge_via_vt8237r_config *)dev->chip_info; u8 enables; u32 cablesel; diff --git a/src/northbridge/via/vx800/vx800_lpc.c b/src/northbridge/via/vx800/vx800_lpc.c index 92660212cf..8f79670034 100644 --- a/src/northbridge/via/vx800/vx800_lpc.c +++ b/src/northbridge/via/vx800/vx800_lpc.c @@ -30,28 +30,28 @@ #include "vx800.h" #include "chip.h" -static const unsigned char pciIrqs[4] = {0xa, 0x9, 0xb, 0xa}; +static const unsigned char pciIrqs[4] = { 0xa, 0x9, 0xb, 0xa }; -static const unsigned char vgaPins[4] = { 'A', 'B', 'C', 'D' };//only INTA +static const unsigned char vgaPins[4] = { 'A', 'B', 'C', 'D' }; //only INTA -static const unsigned char slotPins[4] = { 'A', 'A', 'A', 'A'};//all 4 +static const unsigned char slotPins[4] = { 'A', 'A', 'A', 'A' }; //all 4 -static const unsigned char usbdevicePins[4] = { 'A', 'B', 'C', 'D' };//only INTA -static const unsigned char sdioPins[4] = { 'A', 'B', 'C', 'D' };//only INTA -static const unsigned char sd_ms_ctrl_Pins[4] = { 'B', 'C', 'D', 'A' };//only INTA -static const unsigned char ce_ata_nf_ctrl_Pins[4] = { 'C', 'C', 'D', 'A' };//only INTA -static const unsigned char idePins[4] = { 'B', 'C', 'D', 'A' };//only INTA +static const unsigned char usbdevicePins[4] = { 'A', 'B', 'C', 'D' }; //only INTA +static const unsigned char sdioPins[4] = { 'A', 'B', 'C', 'D' }; //only INTA +static const unsigned char sd_ms_ctrl_Pins[4] = { 'B', 'C', 'D', 'A' }; //only INTA +static const unsigned char ce_ata_nf_ctrl_Pins[4] = { 'C', 'C', 'D', 'A' }; //only INTA +static const unsigned char idePins[4] = { 'B', 'C', 'D', 'A' }; //only INTA -static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' };//all 4 +static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' }; //all 4 -static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' };//only INTA +static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' }; //only INTA static unsigned char *pin_to_irq(const unsigned char *pin) { static unsigned char Irqs[4]; int i; - for (i = 0 ; i < 4 ; i++) - Irqs[i] = pciIrqs[ pin[i] - 'A' ]; + for (i = 0; i < 4; i++) + Irqs[i] = pciIrqs[pin[i] - 'A']; return Irqs; } @@ -62,7 +62,7 @@ static void pci_routing_fixup(struct device *dev) /* set up PCI IRQ routing */ pci_write_config8(dev, 0x55, pciIrqs[0] << 4); - pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) ); + pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4)); pci_write_config8(dev, 0x57, pciIrqs[3] << 4); /* VGA */ @@ -95,7 +95,7 @@ static void pci_routing_fixup(struct device *dev) /* Standard usb components */ printk_info("setting usb1-2\n"); -// pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); +// pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); /* sound hardware */ printk_info("setting hdac audio\n"); @@ -111,27 +111,27 @@ void setup_pm(device_t dev) pci_write_config8(dev, 0x80, 0x20); /* Set ACPI base address to IO VX800_ACPI_IO_BASE */ - pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE|1); + pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 1); /* set ACPI irq to 9 */ pci_write_config8(dev, 0x82, 0x49); /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ -// pci_write_config16(dev, 0x84, 0x30f2); - pci_write_config16(dev, 0x84, 0x609a); // 0x609a?? +// pci_write_config16(dev, 0x84, 0x30f2); + pci_write_config16(dev, 0x84, 0x609a); // 0x609a?? /* SMI output level to low, 7.5us throttle clock */ pci_write_config8(dev, 0x8d, 0x18); /* GP Timer Control 1s */ pci_write_config8(dev, 0x93, 0x88); - + /* Power Well */ pci_write_config8(dev, 0x94, 0x20); // 0x20?? /* 7 = stp to sust delay 1msec - * 6 = SUSST# Deasserted Before PWRGD for STD - */ + * 6 = SUSST# Deasserted Before PWRGD for STD + */ pci_write_config8(dev, 0x95, 0xc0); // 0xc1?? /* Disable GP2 & GP3 Timer */ @@ -147,7 +147,6 @@ void setup_pm(device_t dev) /* Multi Function Select 2 */ pci_write_config8(dev, 0xe5, 0x41); //?? - /* Enable ACPI access (and setup like award) */ pci_write_config8(dev, 0x81, 0x84); @@ -198,39 +197,41 @@ void setup_pm(device_t dev) outw(0x001, 0x404); */ } + void S3_ps2_kb_ms_wakeup(struct device *dev) -{ u8 enables; +{ + u8 enables; enables = pci_read_config8(dev, 0x51); enables |= 2; pci_write_config8(dev, 0x51, enables); - + outb(0xe0, 0x2e); - outb(0x0b, 0x2f);//if 09,then only support kb wakeup + outb(0x0b, 0x2f); //if 09,then only support kb wakeup - outb(0xe1, 0x2e);//set any key scan code can wakeup + outb(0xe1, 0x2e); //set any key scan code can wakeup outb(0x00, 0x2f); - - outb(0xe9, 0x2e);//set any mouse scan code can wakeup + + outb(0xe9, 0x2e); //set any mouse scan code can wakeup outb(0x00, 0x2f); enables &= 0xd; pci_write_config8(dev, 0x51, enables); - outb(inb(VX800_ACPI_IO_BASE+0x02)|0x20, VX800_ACPI_IO_BASE+0x02);//ACPI golabe enable for sci smi trigger - outw(inw(VX800_ACPI_IO_BASE+0x22)|0x204, VX800_ACPI_IO_BASE+0x22);//ACPI SCI on Internal KBC PME and mouse PME - + outb(inb(VX800_ACPI_IO_BASE + 0x02) | 0x20, VX800_ACPI_IO_BASE + 0x02); //ACPI golabe enable for sci smi trigger + outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x204, VX800_ACPI_IO_BASE + 0x22); //ACPI SCI on Internal KBC PME and mouse PME + } + void S3_usb_wakeup(struct device *dev) { - outw(inw(VX800_ACPI_IO_BASE+0x22)|0x4000, VX800_ACPI_IO_BASE+0x22);//SCI on USB PME + outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x4000, VX800_ACPI_IO_BASE + 0x22); //SCI on USB PME } void S3_lid_wakeup(struct device *dev) { - outw(inw(VX800_ACPI_IO_BASE+0x22)|0x800, VX800_ACPI_IO_BASE+0x22);//SCI on LID PME + outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x800, VX800_ACPI_IO_BASE + 0x22); //SCI on LID PME } - /* This looks good enough to work, maybe */ static void vx800_sb_init(struct device *dev) { @@ -242,7 +243,7 @@ static void vx800_sb_init(struct device *dev) pci_write_config8(dev, 0x6C, enables); // Map 4MB of FLASH into the address space -// pci_write_config8(dev, 0x41, 0x7f); +// pci_write_config8(dev, 0x41, 0x7f); // Set bit 6 of 0x40, because Award does it (IO recovery time) // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI @@ -260,7 +261,7 @@ static void vx800_sb_init(struct device *dev) pci_write_config8(dev, 0x4c, 0x44); /* ROM memory cycles go to LPC. */ - pci_write_config8(dev, 0x59, 0x80); + pci_write_config8(dev, 0x59, 0x80); /* Set 0x5b to 0x01 to match Award */ //pci_write_config8(dev, 0x5b, 0x01); @@ -268,16 +269,14 @@ static void vx800_sb_init(struct device *dev) enables |= 0x01; pci_write_config8(dev, 0x5b, enables); - /* Set Read Pass Write Control Enable */ pci_write_config8(dev, 0x48, 0x0c); /* Set 0x58 to 0x42 APIC and RTC. */ //pci_write_config8(dev, 0x58, 0x42); this cmd cause the irq0 can not be triggerd,since bit 5 was set to 0. - enables=pci_read_config8(dev, 0x58); - enables|=0x41;// - pci_write_config8(dev, 0x58,enables); - + enables = pci_read_config8(dev, 0x58); + enables |= 0x41; // + pci_write_config8(dev, 0x58, enables); /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ enables = pci_read_config8(dev, 0x4f); @@ -308,21 +307,24 @@ void vx800_read_resources(device_t dev) struct resource *resource; pci_dev_read_resources(dev); resource = new_resource(dev, 1); - resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO | IORESOURCE_STORED; + resource->flags |= + IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO | + IORESOURCE_STORED; resource->size = 2; resource->base = 0x2e; } + void vx800_set_resources(device_t dev) { struct resource *resource; - resource = find_resource(dev,1); + resource = find_resource(dev, 1); resource->flags |= IORESOURCE_STORED; pci_dev_set_resources(dev); } void vx800_enable_resources(device_t dev) - { +{ /* vx800 is not a pci bridge and has no resources of its own (other than standard PC i/o addresses). however it does control the isa bus and so we need to manually call enable childrens resources on that bus */ @@ -332,18 +334,19 @@ void vx800_enable_resources(device_t dev) } static void southbridge_init(struct device *dev) -{ +{ printk_debug("vx800 sb init\n"); vx800_sb_init(dev); pci_routing_fixup(dev); - setup_i8259(); // make sure interupt controller is configured before keyboard init + setup_i8259(); // make sure interupt controller is configured before keyboard init - /* turn on keyboard and RTC, no need to visit this reg twice */ + /* turn on keyboard and RTC, no need to visit this reg twice */ init_pc_keyboard(0x60, 0x64, 0); - printk_debug("ps2 usb lid, you set who can wakeup system from s3 sleep\n"); + printk_debug + ("ps2 usb lid, you set who can wakeup system from s3 sleep\n"); S3_ps2_kb_ms_wakeup(dev); - S3_usb_wakeup(dev); + S3_usb_wakeup(dev); /* enable acpi cpu c3 state. (c2 state need not do anything.) #1 @@ -370,15 +373,15 @@ static void southbridge_init(struct device *dev) } static struct device_operations vx800_lpc_ops = { - .read_resources = vx800_read_resources, - .set_resources = vx800_set_resources, + .read_resources = vx800_read_resources, + .set_resources = vx800_set_resources, .enable_resources = vx800_enable_resources, - .init = &southbridge_init, - .scan_bus = scan_static_bus, + .init = &southbridge_init, + .scan_bus = scan_static_bus, }; static struct pci_driver lpc_driver __pci_driver = { - .ops = &vx800_lpc_ops, + .ops = &vx800_lpc_ops, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VX855_LPC, }; |