diff options
| author | Shelley Chen <shchen@google.com> | 2024-01-09 22:10:17 -0800 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2024-01-23 04:57:35 +0000 |
| commit | 72f95ad0522b1a51773551c46988495dba6a1128 (patch) | |
| tree | 2bb976ed3705a326a5f3119f1af5163bb3b97ecc | |
| parent | e4fb5e7155075c2c0b2f5cdb3ba6f0f6a4d559ae (diff) | |
mb/google/brox: Enable WLAN on root port 5
BUG=b:311450057,b:300690448,b:319188820
BRANCH=None
TEST=test on device with lspci
& make sure can see the Intel Network controller
Change-Id: I361bef13ebd073b6fccb729a1960d3832cf2681a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
| -rw-r--r-- | src/mainboard/google/brox/variants/brox/overridetree.cb | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index 1962279c8c..dc1866323f 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -181,6 +181,20 @@ chip soc/intel/alderlake }" probe STORAGE STORAGE_NVME end + device ref pcie_rp5 on + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" + register "srcclk_pin" = "1" + device generic 0 on end + end + probe WIFI WIFI_PCIE + end device ref ish on chip drivers/intel/ish register "add_acpi_dma_property" = "true" |