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authorRen Kuo <ren.kuo@quanta.corp-partner.google.com>2022-10-28 13:01:22 +0800
committerEric Lai <eric_lai@quanta.corp-partner.google.com>2022-11-07 01:24:45 +0000
commit6ec48057d0f64c4595758df166dc80fb4ae84ba2 (patch)
treec9a72608af89ec6a5da1fc51f82ff830491d3fdd
parent27802bb7b20656f0c4c083a301b9bd6af131a19c (diff)
mb/google/brya/variants/volmar: Add firmware config field for FPMCU
The fingerprint(FP) feature is only for volmar,and it's not for zavala. Add FPMCU_MASK field in fw_config to disable the FP function for zavala, and reserve FP function for shipped volmar. Define the value as following: field FPMCU_MASK 10 option FPMCU_ENABLED 0 option FPMCU_DISABLED 1 end BUG=b:250807253 TEST=build firmware and verify the fp function in volmar DUT. write `disable=1` and 'enable=0' in FPCMU_MASK field. check the fp function and run `ectool --name cros_fp version` It works as expected. Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I867771904811459697056662d5e29c545a1a9474 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68917 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/brya/variants/volmar/overridetree.cb8
-rw-r--r--src/mainboard/google/brya/variants/volmar/variant.c4
2 files changed, 11 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb
index ce5cbdaf81..056467c978 100644
--- a/src/mainboard/google/brya/variants/volmar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb
@@ -19,6 +19,10 @@ fw_config
option BOOT_EMMC_DISABLED 0
option BOOT_EMMC_ENABLED 1
end
+ field FPMCU_MASK 10
+ option FPMCU_ENABLED 0
+ option FPMCU_DISABLED 1
+ end
end
chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
@@ -321,7 +325,9 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
- device spi 0 on end
+ device spi 0 on
+ probe FPMCU_MASK FPMCU_ENABLED
+ end
end # FPMCU
end
device ref pch_espi on
diff --git a/src/mainboard/google/brya/variants/volmar/variant.c b/src/mainboard/google/brya/variants/volmar/variant.c
index 86c65c7ea7..d1ef1fa645 100644
--- a/src/mainboard/google/brya/variants/volmar/variant.c
+++ b/src/mainboard/google/brya/variants/volmar/variant.c
@@ -14,4 +14,8 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
{
config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
MAX98373_NAU88L25B_I2S));
+
+ if (fw_config_probe(FW_CONFIG(FPMCU_MASK, FPMCU_DISABLED)))
+ config->serial_io_gspi_mode[PchSerialIoIndexGSPI1] = PchSerialIoDisabled;
+
}