diff options
| author | Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> | 2024-10-23 12:41:02 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-10-24 03:28:05 +0000 |
| commit | 6d2048443eb2ee5e8eaf0f6040be95f86932ca25 (patch) | |
| tree | 3cac3a4e14ab463bbd249f7bfdd52e305704dc61 | |
| parent | 144cd4223be992177bef203a31db20fba7d7ad80 (diff) | |
mb/google/brya/var/nova: Disable Thunderbolt device
Nova doesn't support thunderbolt, so disable the TBT setting.
Enabling TBT also causes the system to fail to enter S3/S5 state.
S5 fail log:
24-10-21 20:23:34.610 Port 80 writes:
24-10-21 20:23:34.610 9a02 9a32 9a14 9c15 9c18 9c19 9c20 9c22 9c25 9c28 9c3f 9c43 9c44 9c4f 9c23 9a50 9a5f 9a33 9b40 9b41
24-10-21 20:23:34.620 9b42 9b47 9c80 9c81 9c82 9c83 9a61 9a63 9a03 9a04 9a05 9a06 9a07 9a0f 9a65 9a64 9c6a 9c71 9c7f 99
24-10-21 20:23:34.626 a0 a1 72 24 25 24 25 55 24 25 55 55 73 74 75 75 75 75 75 75
24-10-21 20:23:34.633 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
24-10-21 20:23:34.639 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
24-10-21 20:23:34.643 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 76 77 79 9c
24-10-21 20:23:34.649 93 7a fe 7b f8 aa ab 96 <--new
powerinfo
24-10-21 20:23:59.424 powerinfo
24-10-21 20:23:59.424 power state 4 = S0, in 0x00ff
The correct power state for S5 is G3, not S0.
BUG=b:374213121
TEST=emerge-constitution coreboot chromeos-bootimage. Booting to OS and verify S3/S5 by EC log.
Change-Id: I2bae8ae396f001dbef3322e361f9563792e1a1ef
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84838
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/nova/overridetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb index 500564425a..bf517c87b0 100644 --- a/src/mainboard/google/brya/variants/nova/overridetree.cb +++ b/src/mainboard/google/brya/variants/nova/overridetree.cb @@ -257,6 +257,10 @@ chip soc/intel/alderlake end end device ref pmc hidden end + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + device ref tbt_pcie_rp3 off end device ref tcss_xhci on end device ref tcss_dma0 off end device ref tcss_dma1 off end |