diff options
| author | Patrick Georgi <pgeorgi@google.com> | 2021-02-12 13:49:11 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-15 11:30:40 +0000 |
| commit | 6b688f5329e560ef432f6ea281b2fe3d905ef297 (patch) | |
| tree | 831ff654f7477b293421e38b8ed880f2cc740386 | |
| parent | 036d66be051c4aeeac3b6220974e93645489c27d (diff) | |
src: use ARRAY_SIZE where possible
Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci
Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
74 files changed, 214 insertions, 208 deletions
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index e38feed5cf..3ef878f517 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -123,7 +123,7 @@ static const char *cpu_vendor_name(int vendor) { const char *name; name = "<invalid CPU vendor>"; - if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && + if ((vendor < ARRAY_SIZE(x86_vendor_name)) && (x86_vendor_name[vendor] != 0)) name = x86_vendor_name[vendor]; return name; diff --git a/src/cpu/x86/smm/smm_module_loaderv2.c b/src/cpu/x86/smm/smm_module_loaderv2.c index 715ea0afc7..cd44f93cc9 100644 --- a/src/cpu/x86/smm/smm_module_loaderv2.c +++ b/src/cpu/x86/smm/smm_module_loaderv2.c @@ -129,7 +129,7 @@ static int smm_create_map(uintptr_t smbase, unsigned int num_cpus, return 0; } - if (sizeof(cpus) / sizeof(struct cpu_smm_info) < num_cpus) { + if (ARRAY_SIZE(cpus) < num_cpus) { printk(BIOS_ERR, "%s: increase MAX_CPUS in Kconfig\n", __func__); return 0; diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 69b0c9db14..9e5e81fc21 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -98,7 +98,7 @@ static const struct pirq_struct mainboard_pirq_data[] = { static void pirq_setup(void) { pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } diff --git a/src/mainboard/asus/am1i-a/mainboard.c b/src/mainboard/asus/am1i-a/mainboard.c index b17030a98a..c028c01e7e 100644 --- a/src/mainboard/asus/am1i-a/mainboard.c +++ b/src/mainboard/asus/am1i-a/mainboard.c @@ -71,7 +71,7 @@ const u8 *intr_data = mainboard_intr_data; static void pirq_setup(void) { pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } diff --git a/src/mainboard/bap/ode_e20XX/mainboard.c b/src/mainboard/bap/ode_e20XX/mainboard.c index 6db8bb6870..38c8a1e71d 100644 --- a/src/mainboard/bap/ode_e20XX/mainboard.c +++ b/src/mainboard/bap/ode_e20XX/mainboard.c @@ -86,7 +86,7 @@ const u8 *intr_data = mainboard_intr_data; static void pirq_setup(void) { pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } diff --git a/src/mainboard/biostar/am1ml/mainboard.c b/src/mainboard/biostar/am1ml/mainboard.c index 37a13bbfcf..f371a44318 100644 --- a/src/mainboard/biostar/am1ml/mainboard.c +++ b/src/mainboard/biostar/am1ml/mainboard.c @@ -75,7 +75,7 @@ const u8 *intr_data = mainboard_intr_data; static void pirq_setup(void) { pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c index 69b0c9db14..9e5e81fc21 100644 --- a/src/mainboard/elmex/pcm205400/mainboard.c +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -98,7 +98,7 @@ static const struct pirq_struct mainboard_pirq_data[] = { static void pirq_setup(void) { pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } diff --git a/src/mainboard/gizmosphere/gizmo2/mainboard.c b/src/mainboard/gizmosphere/gizmo2/mainboard.c index 32a67f8502..c08528a20f 100644 --- a/src/mainboard/gizmosphere/gizmo2/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo2/mainboard.c @@ -85,7 +85,7 @@ const u8 *intr_data = mainboard_intr_data; static void pirq_setup(void) { pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } diff --git a/src/mainboard/google/foster/sdram_configs.c b/src/mainboard/google/foster/sdram_configs.c index 17874b4aeb..25d64036fa 100644 --- a/src/mainboard/google/foster/sdram_configs.c +++ b/src/mainboard/google/foster/sdram_configs.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/bsd/helpers.h> #include <console/console.h> #include <soc/sdram_configs.h> @@ -19,7 +20,7 @@ const struct sdram_params *get_sdram_config() */ printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode); - if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) || + if (ramcode >= ARRAY_SIZE(sdram_configs) || sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) { die("Invalid RAMCODE."); } diff --git a/src/mainboard/google/nyan/sdram_configs.c b/src/mainboard/google/nyan/sdram_configs.c index 74d5660320..241fbce5b3 100644 --- a/src/mainboard/google/nyan/sdram_configs.c +++ b/src/mainboard/google/nyan/sdram_configs.c @@ -33,7 +33,7 @@ const struct sdram_params *get_sdram_config() */ printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode); - if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) || + if (ramcode >= ARRAY_SIZE(sdram_configs) || sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) { die("Invalid RAMCODE."); } diff --git a/src/mainboard/google/nyan_big/sdram_configs.c b/src/mainboard/google/nyan_big/sdram_configs.c index 7193d7b4c4..15ed489070 100644 --- a/src/mainboard/google/nyan_big/sdram_configs.c +++ b/src/mainboard/google/nyan_big/sdram_configs.c @@ -33,7 +33,7 @@ const struct sdram_params *get_sdram_config() */ printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode); - if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) || + if (ramcode >= ARRAY_SIZE(sdram_configs) || sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) { die("Invalid RAMCODE."); } diff --git a/src/mainboard/google/nyan_blaze/sdram_configs.c b/src/mainboard/google/nyan_blaze/sdram_configs.c index 89f6ca8968..7972255173 100644 --- a/src/mainboard/google/nyan_blaze/sdram_configs.c +++ b/src/mainboard/google/nyan_blaze/sdram_configs.c @@ -33,7 +33,7 @@ const struct sdram_params *get_sdram_config() */ printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode); - if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) || + if (ramcode >= ARRAY_SIZE(sdram_configs) || sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) { die("Invalid RAMCODE."); } diff --git a/src/mainboard/google/smaug/sdram_configs.c b/src/mainboard/google/smaug/sdram_configs.c index c45b679a27..8d4521168f 100644 --- a/src/mainboard/google/smaug/sdram_configs.c +++ b/src/mainboard/google/smaug/sdram_configs.c @@ -31,7 +31,7 @@ const struct sdram_params *get_sdram_config() */ printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode); - if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) || + if (ramcode >= ARRAY_SIZE(sdram_configs) || sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) { die("Invalid RAMCODE."); } diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c index f375da6097..88de23a77d 100644 --- a/src/mainboard/hp/abm/mainboard.c +++ b/src/mainboard/hp/abm/mainboard.c @@ -70,7 +70,7 @@ static const struct pirq_struct mainboard_pirq_data[] = { static void pirq_setup(void) { pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index c0eb97a2fe..a8ed85dad7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -99,7 +99,7 @@ static const struct pirq_struct mainboard_pirq_data[] = { static void pirq_setup(void) { pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 7e3ef08b48..fa9b093920 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -111,7 +111,7 @@ static const struct pirq_struct mainboard_pirq_data[] = { static void pirq_setup(void) { pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index bad1a57fd5..062d223860 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -114,7 +114,7 @@ static const struct pirq_struct mainboard_pirq_data[] = { static void pirq_setup(void) { pirq_data_ptr = mainboard_pirq_data; - pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 4822ead662..4a8cf9057a 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -92,7 +92,7 @@ static const uint32_t refresh_rate_map[] = { 1, 7, 2, 1, 1, 3 }; -#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1) +#define MAX_SPD_REFRESH_RATE (ARRAY_SIZE(refresh_rate_map) - 1) // SPD parameters that must match for dual-channel operation static const uint8_t dual_channel_parameters[] = { diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index c3d1b0d15f..407be5585e 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3770,8 +3770,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) continue; for (addr = 0; addr < - sizeof(useful_addresses) / - sizeof(useful_addresses[0]); addr++) + ARRAY_SIZE(useful_addresses); addr++) gav(info. spd[channel][0][useful_addresses [addr]] = diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index ae0cce3cae..5c10dd58d0 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -20,7 +20,7 @@ unsigned int cpu_bus_freq_khz(void) { msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); - if ((clk_info.lo & 0xf) < (sizeof(cpu_bus_clk_freq_table) / sizeof(unsigned int))) + if ((clk_info.lo & 0xf) < ARRAY_SIZE(cpu_bus_clk_freq_table)) return cpu_bus_clk_freq_table[clk_info.lo & 0xf]; return 0; diff --git a/src/soc/intel/denverton_ns/gpio_dnv.c b/src/soc/intel/denverton_ns/gpio_dnv.c index 0999cce4cd..70138d3ed7 100644 --- a/src/soc/intel/denverton_ns/gpio_dnv.c +++ b/src/soc/intel/denverton_ns/gpio_dnv.c @@ -59,8 +59,7 @@ static const struct GPIO_GROUP_INFO mGpioGroupInfo[] = { static struct GPIO_GROUP_INFO * GpioGetGroupInfoTable(uint32_t *GpioGroupInfoTableLength) { - *GpioGroupInfoTableLength = - sizeof(mGpioGroupInfo) / sizeof(struct GPIO_GROUP_INFO); + *GpioGroupInfoTableLength = ARRAY_SIZE(mGpioGroupInfo); return (struct GPIO_GROUP_INFO *)mGpioGroupInfo; } diff --git a/src/soc/qualcomm/sc7180/display/dsi_phy.c b/src/soc/qualcomm/sc7180/display/dsi_phy.c index 050a5d88f1..db4b67cfe7 100644 --- a/src/soc/qualcomm/sc7180/display/dsi_phy.c +++ b/src/soc/qualcomm/sc7180/display/dsi_phy.c @@ -564,7 +564,7 @@ static unsigned long dsi_phy_calc_clk_divider(struct dsi_phy_configtype *phy_cfg /* D Phy */ lut = pll_dividerlut_dphy; - lut_max = sizeof(pll_dividerlut_dphy) / sizeof(*lut); + lut_max = ARRAY_SIZE(pll_dividerlut_dphy); lut += (lut_max - 1); /* PLL Post Div - from LUT diff --git a/src/vendorcode/amd/agesa/common/agesa-entry.c b/src/vendorcode/amd/agesa/common/agesa-entry.c index 1e861497ad..42f12b3950 100644 --- a/src/vendorcode/amd/agesa/common/agesa-entry.c +++ b/src/vendorcode/amd/agesa/common/agesa-entry.c @@ -105,7 +105,7 @@ CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = { 0, 0, NULL } }; -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); +CONST UINTN InitializerCount = ARRAY_SIZE(FuncParamsInfo); CONST DISPATCH_TABLE ROMDATA DispatchTable[] = { diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c index 263061d164..1c1a3a7971 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c @@ -315,7 +315,7 @@ CONST PROC_FAMILY_TABLE ROMDATA ProcFamily14DmiTable = &DmiF14GetMaxSpeed, &DmiF14GetExtClock, &DmiF14GetMemInfo, // Get memory information - (sizeof (Family14BrandList) / sizeof (Family14BrandList[0])), // Number of entries in following table + ARRAY_SIZE(Family14BrandList), // Number of entries in following table &Family14BrandList[0] }; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c index 4adb54f265..1694a93cd9 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c @@ -154,7 +154,7 @@ F14PmPwrPlaneInit ( // Next, round it to the appropriate encoded value. We will start from encoding 111b which corresponds // to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable // VRM can be. - for (VSRampSlamTime = ((sizeof (F14VSRampSlamWaitTimes) / sizeof (F14VSRampSlamWaitTimes[0])) - 1); VSRampSlamTime > 0; VSRampSlamTime--) { + for (VSRampSlamTime = (ARRAY_SIZE(F14VSRampSlamWaitTimes)- 1); VSRampSlamTime > 0; VSRampSlamTime--) { if (WaitTime <= F14VSRampSlamWaitTimes[VSRampSlamTime]) { break; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c index dd4c69a48e..5531f47ba2 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c @@ -95,7 +95,7 @@ AMD_WHEA_INIT_DATA F14WheaInitData = { 0x00, // AmdMcbClrStatusOnInit 0x02, // AmdMcbStatusDataFormat 0x00, // AmdMcbConfWriteEn - (sizeof (F14HestBankInitData) / sizeof (F14HestBankInitData[0])), // HestBankNum + ARRAY_SIZE(F14HestBankInitData), // HestBankNum &F14HestBankInitData[0] // Pointer to Initial data of HEST Bank }; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c index a974108f6d..ee83ae738c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c @@ -363,7 +363,7 @@ GMM_REG_ENTRY GmcDisableClockGating[] = { }; TABLE_INDIRECT_PTR GmcDisableClockGatingPtr = { - sizeof (GmcDisableClockGating) / sizeof (GMM_REG_ENTRY), + ARRAY_SIZE(GmcDisableClockGating), GmcDisableClockGating }; @@ -383,7 +383,7 @@ GMM_REG_ENTRY GmcEnableClockGating[] = { TABLE_INDIRECT_PTR GmcEnableClockGatingPtr = { - sizeof (GmcEnableClockGating) / sizeof (GMM_REG_ENTRY), + ARRAY_SIZE(GmcEnableClockGating), GmcEnableClockGating }; @@ -414,7 +414,7 @@ GMM_REG_ENTRY GmcPerformanceTuningTable [] = { }; TABLE_INDIRECT_PTR GmcPerformanceTuningTablePtr = { - sizeof (GmcPerformanceTuningTable) / sizeof (GMM_REG_ENTRY), + ARRAY_SIZE(GmcPerformanceTuningTable), GmcPerformanceTuningTable }; @@ -431,7 +431,7 @@ GMM_REG_ENTRY GmcMiscInitTable [] = { }; TABLE_INDIRECT_PTR GmcMiscInitTablePtr = { - sizeof (GmcMiscInitTable) / sizeof (GMM_REG_ENTRY), + ARRAY_SIZE(GmcMiscInitTable), GmcMiscInitTable }; @@ -446,7 +446,7 @@ GMM_REG_ENTRY GmcRemoveBlackoutTable [] = { }; TABLE_INDIRECT_PTR GmcRemoveBlackoutTablePtr = { - sizeof (GmcRemoveBlackoutTable) / sizeof (GMM_REG_ENTRY), + ARRAY_SIZE(GmcRemoveBlackoutTable), GmcRemoveBlackoutTable }; @@ -522,7 +522,7 @@ GMM_REG_ENTRY GmcRegisterEngineInitTable [] = { }; TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr = { - sizeof (GmcRegisterEngineInitTable) / sizeof (GMM_REG_ENTRY), + ARRAY_SIZE(GmcRegisterEngineInitTable), GmcRegisterEngineInitTable }; @@ -633,7 +633,7 @@ REGISTER_COPY_ENTRY CnbToGncRegisterCopyTable [] = { TABLE_INDIRECT_PTR CnbToGncRegisterCopyTablePtr = { - sizeof (CnbToGncRegisterCopyTable) / sizeof (REGISTER_COPY_ENTRY), + ARRAY_SIZE(CnbToGncRegisterCopyTable), CnbToGncRegisterCopyTable }; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c index 440c5ff68c..e2480ecde4 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -239,7 +239,7 @@ GfxIntegratedExtConnectorInfo ( ) { UINTN Index; - for (Index = 0; Index < (sizeof (ConnectorInfoTable) / sizeof (EXT_CONNECTOR_INFO)); Index++) { + for (Index = 0; Index < ARRAY_SIZE(ConnectorInfoTable); Index++) { if (ConnectorInfoTable[Index].ConnectorType == ConnectorType) { return &ConnectorInfoTable[Index]; } @@ -317,7 +317,7 @@ GfxIntegratedExtDisplayDeviceInfo ( UINT8 Index; UINT8 LastIndex; LastIndex = 0xff; - for (Index = 0; Index < (sizeof (DisplayDeviceInfoTable) / sizeof (EXT_DISPLAY_DEVICE_INFO)); Index++) { + for (Index = 0; Index < ARRAY_SIZE(DisplayDeviceInfoTable); Index++) { if (DisplayDeviceInfoTable[Index].DisplayDeviceEnum == DisplayDeviceEnum) { LastIndex = Index; if (DisplayDeviceInfoTable[Index].DeviceIndex == DisplayDeviceIndex) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c index 827bd7f3f3..d5c16ae866 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c @@ -209,7 +209,7 @@ NbFmInitLclkDpmRcActivity ( NbSmuRcuRegisterWrite ( 0x84AC, &LclkDpmCacTable[0], - sizeof (LclkDpmCacTable) / sizeof (UINT32), + ARRAY_SIZE(LclkDpmCacTable), TRUE, StdHeader ); @@ -225,7 +225,7 @@ NbFmInitLclkDpmRcActivity ( StdHeader ); // Program sampling period - for (Index = 0; Index < (sizeof (SamplingPeriod) / sizeof (SamplingPeriod[0])); Index = Index + 2) { + for (Index = 0; Index < ARRAY_SIZE(SamplingPeriod); Index = Index + 2) { UINT16 Temp; Temp = SamplingPeriod[Index]; SamplingPeriod[Index] = SamplingPeriod[Index + 1]; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c index d067875aba..dd5e6450ee 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c @@ -687,132 +687,132 @@ FUSE_REGISTER_ENTRY FCRxFE00_70D7_TABLE [] = { FUSE_TABLE_ENTRY FuseRegisterTable [] = { { FCRxFE00_70A2_ADDRESS, - sizeof (FCRxFE00_70A2_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70A2_TABLE), FCRxFE00_70A2_TABLE }, { FCRxFE00_70A4_ADDRESS, - sizeof (FCRxFE00_70A4_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70A4_TABLE), FCRxFE00_70A4_TABLE }, { FCRxFE00_70A5_ADDRESS, - sizeof (FCRxFE00_70A5_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70A5_TABLE), FCRxFE00_70A5_TABLE }, { FCRxFE00_70A8_ADDRESS, - sizeof (FCRxFE00_70A8_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70A8_TABLE), FCRxFE00_70A8_TABLE }, { FCRxFE00_600E_ADDRESS, - sizeof (FCRxFE00_600E_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_600E_TABLE), FCRxFE00_600E_TABLE }, { FCRxFE00_70AA_ADDRESS, - sizeof (FCRxFE00_70AA_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70AA_TABLE), FCRxFE00_70AA_TABLE }, { FCRxFE00_70AE_ADDRESS, - sizeof (FCRxFE00_70AE_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70AE_TABLE), FCRxFE00_70AE_TABLE }, { FCRxFE00_70B1_ADDRESS, - sizeof (FCRxFE00_70B1_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70B1_TABLE), FCRxFE00_70B1_TABLE }, { FCRxFE00_70B4_ADDRESS, - sizeof (FCRxFE00_70B4_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70B4_TABLE), FCRxFE00_70B4_TABLE }, { FCRxFE00_70B5_ADDRESS, - sizeof (FCRxFE00_70B5_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70B5_TABLE), FCRxFE00_70B5_TABLE }, { FCRxFE00_70B8_ADDRESS, - sizeof (FCRxFE00_70B8_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70B8_TABLE), FCRxFE00_70B8_TABLE }, { FCRxFE00_70B9_ADDRESS, - sizeof (FCRxFE00_70B9_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70B9_TABLE), FCRxFE00_70B9_TABLE }, { FCRxFE00_70BC_ADDRESS, - sizeof (FCRxFE00_70BC_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70BC_TABLE), FCRxFE00_70BC_TABLE }, { FCRxFE00_70BF_ADDRESS, - sizeof (FCRxFE00_70BF_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70BF_TABLE), FCRxFE00_70BF_TABLE }, { FCRxFE00_70C0_ADDRESS, - sizeof (FCRxFE00_70C0_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70C0_TABLE), FCRxFE00_70C0_TABLE }, { FCRxFE00_70C1_ADDRESS, - sizeof (FCRxFE00_70C1_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70C1_TABLE), FCRxFE00_70C1_TABLE }, { FCRxFE00_70C4_ADDRESS, - sizeof (FCRxFE00_70C4_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70C4_TABLE), FCRxFE00_70C4_TABLE }, { FCRxFE00_70C7_ADDRESS, - sizeof (FCRxFE00_70C7_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70C7_TABLE), FCRxFE00_70C7_TABLE }, { FCRxFE00_70C8_ADDRESS, - sizeof (FCRxFE00_70C8_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70C8_TABLE), FCRxFE00_70C8_TABLE }, { FCRxFE00_70C9_ADDRESS, - sizeof (FCRxFE00_70C9_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70C9_TABLE), FCRxFE00_70C9_TABLE }, { FCRxFE00_70CC_ADDRESS, - sizeof (FCRxFE00_70CC_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70CC_TABLE), FCRxFE00_70CC_TABLE }, { FCRxFE00_70CF_ADDRESS, - sizeof (FCRxFE00_70CF_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70CF_TABLE), FCRxFE00_70CF_TABLE }, { FCRxFE00_70D2_ADDRESS, - sizeof (FCRxFE00_70D2_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70D2_TABLE), FCRxFE00_70D2_TABLE }, { FCRxFE00_70D4_ADDRESS, - sizeof (FCRxFE00_70D4_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70D4_TABLE), FCRxFE00_70D4_TABLE }, { FCRxFE00_70D7_ADDRESS, - sizeof (FCRxFE00_70D7_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + ARRAY_SIZE(FCRxFE00_70D7_TABLE), FCRxFE00_70D7_TABLE }, }; FUSE_TABLE FuseTable = { - sizeof (FuseRegisterTable) / sizeof (FUSE_TABLE_ENTRY), + ARRAY_SIZE(FuseRegisterTable), FuseRegisterTable }; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c index aec468659f..01feea4c7f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c @@ -477,7 +477,7 @@ PcieFmPreInit ( PcieFmExecuteNativeGen1Reconfig (Pcie); } Silicon = PcieComplexGetSiliconList (&Pcie->ComplexList[0]); - for (Index = 0; Index < (sizeof (PcieInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)); Index++) { + for (Index = 0; Index < ARRAY_SIZE(PcieInitTable); Index++) { PcieSiliconRegisterRMW ( Silicon, PcieInitTable[Index].Reg, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c index b83afea231..318bb82566 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c @@ -198,7 +198,7 @@ PcieCommonCoreInit ( if (PcieLibIsPcieWrapper (Wrapper)) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Enter\n"); for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { - for (Index = 0; Index < sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY); Index++) { + for (Index = 0; Index < ARRAY_SIZE(CoreInitTable); Index++) { UINT32 Value; Value = PcieRegisterRead ( Wrapper, diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c index aebec59e86..7dc58d00bc 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c @@ -240,7 +240,7 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorON[] = { CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefON = { 0, - (sizeof (S3PciPreSelfRefDescriptorON) / sizeof (PCI_REG_DESCRIPTOR)), + ARRAY_SIZE(S3PciPreSelfRefDescriptorON), S3PciPreSelfRefDescriptorON, PciSpecialCaseFuncON }; @@ -293,7 +293,7 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorON[] = { CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefON = { 0, - (sizeof (S3CPciPostSelfDescriptorON) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + ARRAY_SIZE(S3CPciPostSelfDescriptorON), S3CPciPostSelfDescriptorON, PciSpecialCaseFuncON }; @@ -307,7 +307,7 @@ MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorON[] = { CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefON = { 0, - (sizeof (S3MSRPreSelfRefDescriptorON) / sizeof (MSR_REG_DESCRIPTOR)), + ARRAY_SIZE(S3MSRPreSelfRefDescriptorON), S3MSRPreSelfRefDescriptorON, NULL }; diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c index 64099f20d1..485d32dc96 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c @@ -209,12 +209,12 @@ MemConstructTechBlock3 ( // // Initialize the SPD pointers for each Dimm // - for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) { + for (i = 0 ; i < ARRAY_SIZE(ChannelPtr->DimmSpdPtr); i++) { ChannelPtr->DimmSpdPtr[i] = NULL; } for (i = 0 ; i < DimmSlots; i++) { ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]); - if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) { + if ( (i + 2) < ARRAY_SIZE(ChannelPtr->DimmSpdPtr)) { if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) { if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_RANKS] >> 3) & 0x07) + 1) > 2) { ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c index 16487bf918..feadd8ba7d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c @@ -150,7 +150,7 @@ F15TnPmPwrPlaneInit ( // Next, round it to the appropriate encoded value. We will start from encoding 111b which corresponds // to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable // VRM can be. - for (VSRampSlamTime = ((sizeof (F15TnVSRampSlamWaitTimes) / sizeof (F15TnVSRampSlamWaitTimes[0])) - 1); VSRampSlamTime > 0; VSRampSlamTime--) { + for (VSRampSlamTime = (ARRAY_SIZE(F15TnVSRampSlamWaitTimes)- 1); VSRampSlamTime > 0; VSRampSlamTime--) { if (WaitTime <= F15TnVSRampSlamWaitTimes[VSRampSlamTime]) { break; } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c index 2f8a90539d..b6a10a48c9 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c @@ -97,7 +97,7 @@ AMD_WHEA_INIT_DATA F15WheaInitData = { 0x00, // AmdMcbClrStatusOnInit 0x02, // AmdMcbStatusDataFormat 0x00, // AmdMcbConfWriteEn - (sizeof (F15HestBankInitData) / sizeof (F15HestBankInitData[0])), // HestBankNum + ARRAY_SIZE(F15HestBankInitData), // HestBankNum &F15HestBankInitData[0] // Pointer to Initial data of HEST Bank }; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c index 1cfddbea63..98d8d2908a 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c @@ -211,7 +211,8 @@ ProgramFchEnvHwAcpiPciReg ( // //Early post initialization of pci config space // - ProgramPciByteTable ((REG8_MASK*) (&FchHudson2InitEnvHwAcpiPciTable[0]), sizeof (FchHudson2InitEnvHwAcpiPciTable) / sizeof (REG8_MASK), StdHeader); + ProgramPciByteTable ((REG8_MASK*) (&FchHudson2InitEnvHwAcpiPciTable[0]), + ARRAY_SIZE(FchHudson2InitEnvHwAcpiPciTable), StdHeader); if ( LocalCfgPtr->Smbus.SmbusSsid != 0 ) { RwPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Smbus.SmbusSsid, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c index ebb53bec88..fefc651130 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c @@ -90,7 +90,7 @@ STATIC PCI_IRQ_REG_BLOCK FchInternalDeviceIrqForApicMode[] = { { (FCH_IRQ_GPPINT3 | FCH_IRQ_IOAPIC), 0x13}, }; -#define NUM_OF_DEVICE_FOR_APICIRQ sizeof (FchInternalDeviceIrqForApicMode) / sizeof (PCI_IRQ_REG_BLOCK) +#define NUM_OF_DEVICE_FOR_APICIRQ ARRAY_SIZE(FchInternalDeviceIrqForApicMode) /** * FchInitLateHwAcpi - Prepare HwAcpi controller to boot to OS. diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c index 28ab4261d0..fa185d1568 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c @@ -88,7 +88,8 @@ FchInitEnvPcib ( // //Early post initialization of pci config space // - ProgramPciByteTable ((REG8_MASK*) (&FchInitEnvPcibPciTable[0]), sizeof (FchInitEnvPcibPciTable) / sizeof (REG8_MASK), StdHeader); + ProgramPciByteTable ((REG8_MASK*) (&FchInitEnvPcibPciTable[0]), + ARRAY_SIZE(FchInitEnvPcibPciTable), StdHeader); // //Disable or Enable PCI Clks based on input diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c index 173a278b9e..bdb214df42 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c @@ -82,7 +82,7 @@ FchInitResetPcib ( ProgramPciByteTable ( (REG8_MASK*) (&FchInitResetPcibPciTable[0]), - sizeof (FchInitResetPcibPciTable) / sizeof (REG8_MASK), + ARRAY_SIZE(FchInitResetPcibPciTable), StdHeader ); if ( UserOptions.FchBldCfg->CfgFchPort80BehindPcib ) { @@ -129,7 +129,7 @@ FchInitResetPcibPort80Enable ( ProgramPciByteTable ( (REG8_MASK*) (&FchInitResetPcibPort80EnableTable[0]), - sizeof (FchInitResetPcibPort80EnableTable) / sizeof (REG8_MASK), + ARRAY_SIZE(FchInitResetPcibPort80EnableTable), StdHeader ); } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c index 26ff51ddfc..5cec9bede4 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c @@ -211,7 +211,7 @@ FchProgramSataPhy ( PhyTablePtr = &SataPhyTable[0]; - for (Index = 0; Index < (sizeof (SataPhyTable) / sizeof (SATA_PHY_SETTING)); Index++) { + for (Index = 0; Index < ARRAY_SIZE(SataPhyTable); Index++) { RwPci ((SATA_BUS_DEV_FUN << 16) + 0x80, AccessWidth16, 0x00, PhyTablePtr->PhyCoreControlWord, StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + 0x98, AccessWidth32, 0x00, PhyTablePtr->PhyFineTuneDword, StdHeader); ++PhyTablePtr; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c index b1ae0c81f9..b6806317f2 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c @@ -82,7 +82,8 @@ FchInitEnvLpcProgram ( LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; - ProgramPciByteTable ((REG8_MASK*) (&FchInitHudson2EnvLpcPciTable[0]), sizeof (FchInitHudson2EnvLpcPciTable) / sizeof (REG8_MASK), StdHeader); + ProgramPciByteTable ((REG8_MASK*) (&FchInitHudson2EnvLpcPciTable[0]), + ARRAY_SIZE(FchInitHudson2EnvLpcPciTable), StdHeader); // // Disable LPC A-Link Cycle Bypass diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c index 36259d3cbc..107e181394 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c @@ -99,7 +99,8 @@ FchInitResetLpcProgram ( // RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader); - ProgramPciByteTable ( (REG8_MASK*) (&FchInitHudson2ResetLpcPciTable[0]), sizeof (FchInitHudson2ResetLpcPciTable) / sizeof (REG8_MASK), StdHeader); + ProgramPciByteTable ( (REG8_MASK*) (&FchInitHudson2ResetLpcPciTable[0]), + ARRAY_SIZE(FchInitHudson2ResetLpcPciTable), StdHeader); // // Enabling ClkRun Function diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c index 2d42063340..66bdad5494 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -253,7 +253,7 @@ GfxIntegratedExtConnectorInfo ( ) { UINTN Index; - for (Index = 0; Index < (sizeof (ConnectorInfoTable) / sizeof (EXT_CONNECTOR_INFO)); Index++) { + for (Index = 0; Index < ARRAY_SIZE(ConnectorInfoTable); Index++) { if (ConnectorInfoTable[Index].ConnectorType == ConnectorType) { return &ConnectorInfoTable[Index]; } @@ -331,7 +331,7 @@ GfxIntegratedExtDisplayDeviceInfo ( UINT8 Index; UINT8 LastIndex; LastIndex = 0xff; - for (Index = 0; Index < (sizeof (DisplayDeviceInfoTable) / sizeof (EXT_DISPLAY_DEVICE_INFO)); Index++) { + for (Index = 0; Index < ARRAY_SIZE(DisplayDeviceInfoTable); Index++) { if (DisplayDeviceInfoTable[Index].DisplayDeviceEnum == DisplayDeviceEnum) { LastIndex = Index; if (DisplayDeviceInfoTable[Index].DeviceIndex == DisplayDeviceIndex) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c index 1bbb397596..422cbae007 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c @@ -759,9 +759,9 @@ GfxPowerPlayBuildVceStateTable ( UINT8 UsedStateBitmap; UsedStateBitmap = 0; // build used state - for (Index = 0; Index < (sizeof (PpWorkspace->PpFuses->VceFlags) / sizeof (PpWorkspace->PpFuses->VceFlags[0])) ; Index++) { + for (Index = 0; Index < ARRAY_SIZE(PpWorkspace->PpFuses->VceFlags); Index++) { UsedStateBitmap |= PpWorkspace->PpFuses->VceFlags[Index]; - for (VceStateIndex = 0; VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / sizeof (PpWorkspace->VceStateArray[0])); VceStateIndex++) { + for (VceStateIndex = 0; VceStateIndex < ARRAY_SIZE(PpWorkspace->VceStateArray); VceStateIndex++) { if ((PpWorkspace->PpFuses->VceFlags[Index] & (1 << VceStateIndex)) != 0) { Sclk = GfxFmCalculateClock (PpWorkspace->PpFuses->SclkDpmDid[PpWorkspace->PpFuses->VceReqSclkSel[Index]], GnbLibGetHeader (PpWorkspace->Gfx)); Vid = PpWorkspace->PpFuses->SclkDpmVid[PpWorkspace->PpFuses->VceReqSclkSel[Index]]; @@ -777,7 +777,7 @@ GfxPowerPlayBuildVceStateTable ( } } //build unused states - for (VceStateIndex = 0; VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / sizeof (PpWorkspace->VceStateArray[0])); VceStateIndex++) { + for (VceStateIndex = 0; VceStateIndex < ARRAY_SIZE(PpWorkspace->VceStateArray); VceStateIndex++) { if ((UsedStateBitmap & (1 << VceStateIndex)) == 0) { PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex = 0; PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex = GfxPowerPlayAddEclkState (PpWorkspace, 0); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c index 75ec2fb387..89d317ea6e 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c @@ -260,7 +260,7 @@ GfxGmcDctMemoryChannelInfoTN ( UINT32 Index; UINT32 Value; - for (Index = 0; Index < (sizeof (DctRegisterTable) / sizeof (DCT_REGISTER_ENTRY)); Index++) { + for (Index = 0; Index < ARRAY_SIZE(DctRegisterTable); Index++) { GnbRegisterReadTN ( DctRegisterTable[Index].RegisterSpaceType, DctRegisterTable[Index].Address, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c index c700a64541..8b388d583e 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c @@ -417,7 +417,7 @@ GnbCacEnablement ( // Program GPU CAC weights - for (Index = 0; Index < (sizeof (CacWeightsTN) / sizeof (CacWeightsTN[0])); Index++) { + for (Index = 0; Index < ARRAY_SIZE(CacWeightsTN); Index++) { GnbRegisterWriteTN (TYPE_D0F0xBC , (0x1f9a0 + (Index * 4)), &CacWeightsTN[Index], 0, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c index 9737bd2930..8c580a07b7 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c @@ -615,175 +615,175 @@ FUSE_TABLE_ENTRY_TN FuseRegisterTableTN [] = { { D0F0xBC_xE0104158_TYPE, D0F0xBC_xE0104158_ADDRESS, - sizeof (D0F0xBC_xE0104158_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0104158_TABLE), D0F0xBC_xE0104158_TABLE }, { D0F0xBC_xE010415B_TYPE, D0F0xBC_xE010415B_ADDRESS, - sizeof (D0F0xBC_xE010415B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE010415B_TABLE), D0F0xBC_xE010415B_TABLE }, { D0F0xBC_xE0104184_TYPE, D0F0xBC_xE0104184_ADDRESS, - sizeof (D0F0xBC_xE0104184_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0104184_TABLE), D0F0xBC_xE0104184_TABLE }, { D0F0xBC_xE0104187_TYPE, D0F0xBC_xE0104187_ADDRESS, - sizeof (D0F0xBC_xE0104187_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0104187_TABLE), D0F0xBC_xE0104187_TABLE }, { D0F0xBC_xE0104188_TYPE, D0F0xBC_xE0104188_ADDRESS, - sizeof (D0F0xBC_xE0104188_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0104188_TABLE), D0F0xBC_xE0104188_TABLE }, { D0F0xBC_xE0106020_TYPE, D0F0xBC_xE0106020_ADDRESS, - sizeof (D0F0xBC_xE0106020_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0106020_TABLE), D0F0xBC_xE0106020_TABLE }, { D0F0xBC_xE0106023_TYPE, D0F0xBC_xE0106023_ADDRESS, - sizeof (D0F0xBC_xE0106023_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0106023_TABLE), D0F0xBC_xE0106023_TABLE }, { D0F0xBC_xE0106024_TYPE, D0F0xBC_xE0106024_ADDRESS, - sizeof (D0F0xBC_xE0106024_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0106024_TABLE), D0F0xBC_xE0106024_TABLE }, { D0F0xBC_xE010705C_TYPE, D0F0xBC_xE010705C_ADDRESS, - sizeof (D0F0xBC_xE010705C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE010705C_TABLE), D0F0xBC_xE010705C_TABLE }, { D0F0xBC_xE010705F_TYPE, D0F0xBC_xE010705F_ADDRESS, - sizeof (D0F0xBC_xE010705F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE010705F_TABLE), D0F0xBC_xE010705F_TABLE }, { D0F0xBC_xE0107060_TYPE, D0F0xBC_xE0107060_ADDRESS, - sizeof (D0F0xBC_xE0107060_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0107060_TABLE), D0F0xBC_xE0107060_TABLE }, { D0F0xBC_xE0107063_TYPE, D0F0xBC_xE0107063_ADDRESS, - sizeof (D0F0xBC_xE0107063_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0107063_TABLE), D0F0xBC_xE0107063_TABLE }, { D0F0xBC_xE0107064_TYPE, D0F0xBC_xE0107064_ADDRESS, - sizeof (D0F0xBC_xE0107064_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0107064_TABLE), D0F0xBC_xE0107064_TABLE }, { D0F0xBC_xE0107067_TYPE, D0F0xBC_xE0107067_ADDRESS, - sizeof (D0F0xBC_xE0107067_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0107067_TABLE), D0F0xBC_xE0107067_TABLE }, { D0F0xBC_xE0107068_TYPE, D0F0xBC_xE0107068_ADDRESS, - sizeof (D0F0xBC_xE0107068_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0107068_TABLE), D0F0xBC_xE0107068_TABLE }, { D0F0xBC_xE010706B_TYPE, D0F0xBC_xE010706B_ADDRESS, - sizeof (D0F0xBC_xE010706B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE010706B_TABLE), D0F0xBC_xE010706B_TABLE }, { D0F0xBC_xE010706C_TYPE, D0F0xBC_xE010706C_ADDRESS, - sizeof (D0F0xBC_xE010706C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE010706C_TABLE), D0F0xBC_xE010706C_TABLE }, { D0F0xBC_xE010706F_TYPE, D0F0xBC_xE010706F_ADDRESS, - sizeof (D0F0xBC_xE010706F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE010706F_TABLE), D0F0xBC_xE010706F_TABLE }, { D0F0xBC_xE0107070_TYPE, D0F0xBC_xE0107070_ADDRESS, - sizeof (D0F0xBC_xE0107070_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0107070_TABLE), D0F0xBC_xE0107070_TABLE }, { D0F0xBC_xE0107073_TYPE, D0F0xBC_xE0107073_ADDRESS, - sizeof (D0F0xBC_xE0107073_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0107073_TABLE), D0F0xBC_xE0107073_TABLE }, { D0F0xBC_xE0107074_TYPE, D0F0xBC_xE0107074_ADDRESS, - sizeof (D0F0xBC_xE0107074_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0107074_TABLE), D0F0xBC_xE0107074_TABLE }, { D0F0xBC_xE0107077_TYPE, D0F0xBC_xE0107077_ADDRESS, - sizeof (D0F0xBC_xE0107077_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0107077_TABLE), D0F0xBC_xE0107077_TABLE }, { D0F0xBC_xE0107078_TYPE, D0F0xBC_xE0107078_ADDRESS, - sizeof (D0F0xBC_xE0107078_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0107078_TABLE), D0F0xBC_xE0107078_TABLE }, { D0F0xBC_xE010707B_TYPE, D0F0xBC_xE010707B_ADDRESS, - sizeof (D0F0xBC_xE010707B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE010707B_TABLE), D0F0xBC_xE010707B_TABLE }, { D0F0xBC_xE010707C_TYPE, D0F0xBC_xE010707C_ADDRESS, - sizeof (D0F0xBC_xE010707C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE010707C_TABLE), D0F0xBC_xE010707C_TABLE }, { D0F0xBC_xE010707F_TYPE, D0F0xBC_xE010707F_ADDRESS, - sizeof (D0F0xBC_xE010707F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE010707F_TABLE), D0F0xBC_xE010707F_TABLE }, { D0F0xBC_xFF000000_TYPE, D0F0xBC_xFF000000_ADDRESS, - sizeof (D0F0xBC_xFF000000_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xFF000000_TABLE), D0F0xBC_xFF000000_TABLE }, { D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, - sizeof (D0F0xBC_xE0001008_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + ARRAY_SIZE(D0F0xBC_xE0001008_TABLE), D0F0xBC_xE0001008_TABLE } }; FUSE_TABLE_TN FuseTableTN = { - sizeof (FuseRegisterTableTN) / sizeof (FUSE_TABLE_ENTRY_TN), + ARRAY_SIZE(FuseRegisterTableTN), FuseRegisterTableTN }; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c index b1ac093ab1..a58e918a22 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c @@ -110,8 +110,8 @@ STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = { CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN = { &PcieInitEarlyTable[0], - sizeof (PcieInitEarlyTable) / sizeof (PCIE_HOST_REGISTER_ENTRY) -}; + ARRAY_SIZE(PcieInitEarlyTable) + }; STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = { { @@ -160,8 +160,8 @@ STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = { CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN = { &CoreInitTable[0], - sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY) -}; + ARRAY_SIZE(CoreInitTable) + }; STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = { @@ -208,8 +208,8 @@ STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = { CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableTN = { &PortInitEarlyTable[0], - sizeof (PortInitEarlyTable) / sizeof (PCIE_PORT_REGISTER_ENTRY) -}; + ARRAY_SIZE(PortInitEarlyTable) + }; STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = { @@ -227,5 +227,5 @@ STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = { CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN = { &PortInitMidTable[0], - sizeof (PortInitMidTable) / sizeof (PCIE_PORT_REGISTER_ENTRY) -}; + ARRAY_SIZE(PortInitMidTable) + }; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c index a2aa396035..a0a9bb6aab 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c @@ -123,7 +123,7 @@ PcieAspmBlackListFeature ( GnbLibPciRead (LinkAsmp->UpstreamPort.AddressValue, AccessWidth32, &UpstreamDeviceId, StdHeader); GnbLibPciRead (LinkAsmp->DownstreamPort.AddressValue, AccessWidth32, &DownstreamDeviceId, StdHeader); - for (i = 0; i < (sizeof (AspmBrDeviceTable) / sizeof (UINT16)); i = i + 3) { + for (i = 0; i < ARRAY_SIZE(AspmBrDeviceTable); i = i + 3) { VendorId = AspmBrDeviceTable[i]; DeviceId = AspmBrDeviceTable[i + 1]; if (VendorId == (UINT16)UpstreamDeviceId || VendorId == (UINT16)DownstreamDeviceId ) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c index 045315fda4..2bd702a9b3 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c @@ -282,7 +282,7 @@ PciePayloadBlackListFeature ( UINT32 VendorId; GnbLibPciRead (Device.AddressValue, AccessWidth32, &TargetDeviceId, StdHeader); - for (i = 0; i < (sizeof (PayloadBlacklistDeviceTable) / sizeof (UINT16)); i = i + 3) { + for (i = 0; i < ARRAY_SIZE(PayloadBlacklistDeviceTable); i = i + 3) { VendorId = PayloadBlacklistDeviceTable[i]; DeviceId = PayloadBlacklistDeviceTable[i + 1]; if (VendorId == (UINT16)TargetDeviceId) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c index c11e90e30e..c14ab4a8cc 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c @@ -228,7 +228,7 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorTN[] = { CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefTN = { 0, - (sizeof (S3PciPreSelfRefDescriptorTN) / sizeof (PCI_REG_DESCRIPTOR)), + ARRAY_SIZE(S3PciPreSelfRefDescriptorTN), S3PciPreSelfRefDescriptorTN, PciSpecialCaseFuncTN }; @@ -510,7 +510,7 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorTN[] = { CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefTN = { 0, - (sizeof (S3CPciPreSelfDescriptorTN) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + ARRAY_SIZE(S3CPciPreSelfDescriptorTN), S3CPciPreSelfDescriptorTN, PciSpecialCaseFuncTN }; @@ -797,7 +797,7 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorTN[] = { CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefTN = { 0, - (sizeof (S3CPciPostSelfDescriptorTN) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + ARRAY_SIZE(S3CPciPostSelfDescriptorTN), S3CPciPostSelfDescriptorTN, PciSpecialCaseFuncTN }; @@ -811,7 +811,7 @@ MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorTN[] = { CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefTN = { 0, - (sizeof (S3MSRPreSelfRefDescriptorTN) / sizeof (MSR_REG_DESCRIPTOR)), + ARRAY_SIZE(S3MSRPreSelfRefDescriptorTN), S3MSRPreSelfRefDescriptorTN, NULL }; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c index 335934bf5c..dcf62022ab 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c @@ -207,12 +207,12 @@ MemConstructTechBlock3 ( // // Initialize the SPD pointers for each Dimm // - for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) { + for (i = 0 ; i < ARRAY_SIZE(ChannelPtr->DimmSpdPtr); i++) { ChannelPtr->DimmSpdPtr[i] = NULL; } for (i = 0 ; i < DimmSlots; i++) { ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]); - if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) { + if ( (i + 2) < ARRAY_SIZE(ChannelPtr->DimmSpdPtr)) { if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) { if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_RANKS] >> 3) & 0x07) + 1) > 2) { ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c index ab06fe196f..176fd73069 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c @@ -97,7 +97,7 @@ AMD_WHEA_INIT_DATA F16WheaInitData = { 0x00, // AmdMcbClrStatusOnInit 0x02, // AmdMcbStatusDataFormat 0x00, // AmdMcbConfWriteEn - (sizeof (F16HestBankInitData) / sizeof (F16HestBankInitData[0])), // HestBankNum + ARRAY_SIZE(F16HestBankInitData), // HestBankNum &F16HestBankInitData[0] // Pointer to Initial data of HEST Bank }; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c index 57ca222710..9f90a1376c 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c @@ -183,7 +183,8 @@ ProgramFchEnvHwAcpiPciReg ( // //Early post initialization of pci config space // - ProgramPciByteTable ((REG8_MASK*) (&FchYangtzeInitEnvHwAcpiPciTable[0]), sizeof (FchYangtzeInitEnvHwAcpiPciTable) / sizeof (REG8_MASK), StdHeader); + ProgramPciByteTable ((REG8_MASK*) (&FchYangtzeInitEnvHwAcpiPciTable[0]), + ARRAY_SIZE(FchYangtzeInitEnvHwAcpiPciTable), StdHeader); if ( LocalCfgPtr->Smbus.SmbusSsid != 0 ) { RwPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Smbus.SmbusSsid, StdHeader); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiLate.c index db46136bc0..d012d06e13 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiLate.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiLate.c @@ -86,7 +86,7 @@ STATIC PCI_IRQ_REG_BLOCK FchInternalDeviceIrqForApicMode[] = { { (FCH_IRQ_GPPINT3 | FCH_IRQ_IOAPIC), 0x13}, }; -#define NUM_OF_DEVICE_FOR_APICIRQ sizeof (FchInternalDeviceIrqForApicMode) / sizeof (PCI_IRQ_REG_BLOCK) +#define NUM_OF_DEVICE_FOR_APICIRQ ARRAY_SIZE(FchInternalDeviceIrqForApicMode) /** * FchInitLateHwAcpi - Prepare HwAcpi controller to boot to OS. diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c index 0ae09932cf..7cf6a818d7 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c @@ -202,7 +202,7 @@ FchProgramSataPhy ( PhyTablePtr = &SataPhyTable[0]; - for (Index = 0; Index < (sizeof (SataPhyTable) / sizeof (SATA_PHY_SETTING)); Index++) { + for (Index = 0; Index < ARRAY_SIZE(SataPhyTable); Index++) { RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0xFC00, PhyTablePtr->PhyCoreControlWord, StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + 0x98, AccessWidth32, 0x00, PhyTablePtr->PhyFineTuneDword, StdHeader); ++PhyTablePtr; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c index e2f37bbc25..289acd2b00 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c @@ -82,7 +82,8 @@ FchInitEnvLpcProgram ( LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; - ProgramPciByteTable ((REG8_MASK*) (&FchInitYangtzeEnvLpcPciTable[0]), sizeof (FchInitYangtzeEnvLpcPciTable) / sizeof (REG8_MASK), StdHeader); + ProgramPciByteTable ((REG8_MASK*) (&FchInitYangtzeEnvLpcPciTable[0]), + ARRAY_SIZE(FchInitYangtzeEnvLpcPciTable), StdHeader); RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG28, AccessWidth32, (UINT32)~(BIT21 + BIT20 + BIT19), 0); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c index ab71bb9d49..6411e04e38 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c @@ -125,7 +125,8 @@ FchInitResetLpcProgram ( // RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader); - ProgramPciByteTable ( (REG8_MASK*) (&FchInitYangtzeResetLpcPciTable[0]), sizeof (FchInitYangtzeResetLpcPciTable) / sizeof (REG8_MASK), StdHeader); + ProgramPciByteTable ( (REG8_MASK*) (&FchInitYangtzeResetLpcPciTable[0]), + ARRAY_SIZE(FchInitYangtzeResetLpcPciTable), StdHeader); if ( LocalCfgPtr->Spi.LpcClk0 ) { RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGD0 + 1, AccessWidth8, 0xDF, 0x20, StdHeader); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c index 23501227eb..3d3a097e63 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -253,7 +253,7 @@ GfxIntegratedExtConnectorInfo ( ) { UINTN Index; - for (Index = 0; Index < (sizeof (ConnectorInfoTable) / sizeof (EXT_CONNECTOR_INFO)); Index++) { + for (Index = 0; Index < ARRAY_SIZE(ConnectorInfoTable); Index++) { if (ConnectorInfoTable[Index].ConnectorType == ConnectorType) { return &ConnectorInfoTable[Index]; } @@ -331,7 +331,7 @@ GfxIntegratedExtDisplayDeviceInfo ( UINT8 Index; UINT8 LastIndex; LastIndex = 0xff; - for (Index = 0; Index < (sizeof (DisplayDeviceInfoTable) / sizeof (EXT_DISPLAY_DEVICE_INFO)); Index++) { + for (Index = 0; Index < ARRAY_SIZE(DisplayDeviceInfoTable); Index++) { if (DisplayDeviceInfoTable[Index].DisplayDeviceEnum == DisplayDeviceEnum) { LastIndex = Index; if (DisplayDeviceInfoTable[Index].DeviceIndex == DisplayDeviceIndex) { diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c index 4e83c44359..3cc3fad253 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c @@ -889,13 +889,11 @@ GfxPwrPlayBuildVceStateTable ( UsedStateBitmap = 0; // build used state for (Index = 0; - Index < (sizeof (PpWorkspace->PpF1s->VceFlags) / - sizeof (PpWorkspace->PpF1s->VceFlags[0])) ; + Index < ARRAY_SIZE(PpWorkspace->PpF1s->VceFlags); Index++) { UsedStateBitmap |= PpWorkspace->PpF1s->VceFlags[Index]; for (VceStateIndex = 0; - VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / - sizeof (PpWorkspace->VceStateArray[0])); + VceStateIndex < ARRAY_SIZE(PpWorkspace->VceStateArray); VceStateIndex++) { if ((PpWorkspace->PpF1s->VceFlags[Index] & (1 << VceStateIndex)) != 0) { v4 = GfxFmCalculateClock (PpWorkspace->PpF1s->PP_FUSE_ARRAY_V2_fld33[PpWorkspace->PpF1s->PP_FUSE_ARRAY_V2_fld16[Index]], @@ -919,7 +917,7 @@ GfxPwrPlayBuildVceStateTable ( } //build unused states for (VceStateIndex = 0; - VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / sizeof (PpWorkspace->VceStateArray[0])); + VceStateIndex < ARRAY_SIZE(PpWorkspace->VceStateArray); VceStateIndex++) { if ((UsedStateBitmap & (1 << VceStateIndex)) == 0) { PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex = 0; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c index 41b7b176f2..e0dae34ea4 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c @@ -708,157 +708,157 @@ F1_TABLE_ENTRY_KB F1RegisterTableKB [] = { { 0x4, 0xC0104007, - sizeof (D0F0xBC_xC0104007_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0104007_TABLE), D0F0xBC_xC0104007_TABLE }, { 0x4, 0xC0104008, - sizeof (D0F0xBC_xC0104008_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0104008_TABLE), D0F0xBC_xC0104008_TABLE }, { 0x4, 0xC010400c, - sizeof (D0F0xBC_xC010400C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC010400C_TABLE), D0F0xBC_xC010400C_TABLE }, { 0x4, 0xC010407c, - sizeof (D0F0xBC_xC010407C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC010407C_TABLE), D0F0xBC_xC010407C_TABLE }, { 0x4, 0xC0104080, - sizeof (D0F0xBC_xC0104080_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0104080_TABLE), D0F0xBC_xC0104080_TABLE }, { 0x4, 0xC0104083, - sizeof (D0F0xBC_xC0104083_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0104083_TABLE), D0F0xBC_xC0104083_TABLE }, { 0x4, 0xC0104084, - sizeof (D0F0xBC_xC0104084_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0104084_TABLE), D0F0xBC_xC0104084_TABLE }, { 0x4, 0xC0104088, - sizeof (D0F0xBC_xC0104088_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0104088_TABLE), D0F0xBC_xC0104088_TABLE }, { 0x4, 0xC01040a8, - sizeof (D0F0xBC_xC01040A8_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC01040A8_TABLE), D0F0xBC_xC01040A8_TABLE }, { 0x4, 0xC01040ac, - sizeof (D0F0xBC_xC01040AC_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC01040AC_TABLE), D0F0xBC_xC01040AC_TABLE }, { 0x4, 0xC0107044, - sizeof (D0F0xBC_xC0107044_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107044_TABLE), D0F0xBC_xC0107044_TABLE }, { 0x4, 0xC0107064, - sizeof (D0F0xBC_xC0107064_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107064_TABLE), D0F0xBC_xC0107064_TABLE }, { 0x4, 0xC0107067, - sizeof (D0F0xBC_xC0107067_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107067_TABLE), D0F0xBC_xC0107067_TABLE }, { 0x4, 0xC0107068, - sizeof (D0F0xBC_xC0107068_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107068_TABLE), D0F0xBC_xC0107068_TABLE }, { 0x4, 0xC010706b, - sizeof (D0F0xBC_xC010706B_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC010706B_TABLE), D0F0xBC_xC010706B_TABLE }, { 0x4, 0xC010706c, - sizeof (D0F0xBC_xC010706C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC010706C_TABLE), D0F0xBC_xC010706C_TABLE }, { 0x4, 0xC010706f, - sizeof (D0F0xBC_xC010706F_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC010706F_TABLE), D0F0xBC_xC010706F_TABLE }, { 0x4, 0xC0107070, - sizeof (D0F0xBC_xC0107070_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107070_TABLE), D0F0xBC_xC0107070_TABLE }, { 0x4, 0xC0107073, - sizeof (D0F0xBC_xC0107073_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107073_TABLE), D0F0xBC_xC0107073_TABLE }, { 0x4, 0xC0107074, - sizeof (D0F0xBC_xC0107074_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107074_TABLE), D0F0xBC_xC0107074_TABLE }, { 0x4, 0xC0107077, - sizeof (D0F0xBC_xC0107077_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107077_TABLE), D0F0xBC_xC0107077_TABLE }, { 0x4, 0xC0107078, - sizeof (D0F0xBC_xC0107078_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107078_TABLE), D0F0xBC_xC0107078_TABLE }, { 0x4, 0xC010707c, - sizeof (D0F0xBC_xC010707C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC010707C_TABLE), D0F0xBC_xC010707C_TABLE }, { 0x4, 0xC0107080, - sizeof (D0F0xBC_xC0107080_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107080_TABLE), D0F0xBC_xC0107080_TABLE }, { 0x4, 0xC0107083, - sizeof (D0F0xBC_xC0107083_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107083_TABLE), D0F0xBC_xC0107083_TABLE }, { 0x4, 0xC0107084, - sizeof (D0F0xBC_xC0107084_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107084_TABLE), D0F0xBC_xC0107084_TABLE } }; @@ -867,67 +867,67 @@ F1_TABLE_ENTRY_KB PPRegisterTableKB [] = { { D18F3x64_TYPE, D18F3x64_ADDRESS, - sizeof (D18F3x64_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D18F3x64_TABLE), D18F3x64_TABLE }, { 0x4, 0xC0500000, - sizeof (GnbFuseTableKB565_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(GnbFuseTableKB565_TABLE), GnbFuseTableKB565_TABLE }, { D18F2x90_dct0_TYPE, D18F2x90_dct0_ADDRESS, - sizeof (D18F2x90_dct0_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D18F2x90_dct0_TABLE), D18F2x90_dct0_TABLE }, { D18F2x94_dct0_TYPE, D18F2x94_dct0_ADDRESS, - sizeof (D18F2x94_dct0_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D18F2x94_dct0_TABLE), D18F2x94_dct0_TABLE }, { D18F2xA8_dct0_TYPE, D18F2xA8_dct0_ADDRESS, - sizeof (D18F2xA8_dct0_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D18F2xA8_dct0_TABLE), D18F2xA8_dct0_TABLE }, { D18F5x160_TYPE, D18F5x160_ADDRESS, - sizeof (D18F5x160_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D18F5x160_TABLE), D18F5x160_TABLE }, { D18F5x164_TYPE, D18F5x164_ADDRESS, - sizeof (D18F5x164_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D18F5x164_TABLE), D18F5x164_TABLE }, { D18F5x168_TYPE, D18F5x168_ADDRESS, - sizeof (D18F5x168_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D18F5x168_TABLE), D18F5x168_TABLE }, { D18F5x16C_TYPE, D18F5x16C_ADDRESS, - sizeof (D18F5x16C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D18F5x16C_TABLE), D18F5x16C_TABLE } }; F1_TABLE_KB F1TableKB = { - sizeof (F1RegisterTableKB) / sizeof (F1_TABLE_ENTRY_KB), + ARRAY_SIZE(F1RegisterTableKB), F1RegisterTableKB }; F1_TABLE_KB PPTableKB = { - sizeof (PPRegisterTableKB) / sizeof (F1_TABLE_ENTRY_KB), + ARRAY_SIZE(PPRegisterTableKB), PPRegisterTableKB }; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c index bc87ddef3d..4e774a83b6 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c @@ -351,7 +351,7 @@ PcieCheckPortPciDeviceMappingKB ( if (DevFunc == 0) { return TRUE; } - for (Index = 0; Index < (sizeof (DefaultPortDevMap) / sizeof (DefaultPortDevMap[0])); Index++) { + for (Index = 0; Index < ARRAY_SIZE(DefaultPortDevMap); Index++) { if (DefaultPortDevMap[Index] == DevFunc) { return TRUE; } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c index 10f882808a..d99fbe77cc 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c @@ -95,8 +95,8 @@ STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = { CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableKB = { &PcieInitEarlyTable[0], - sizeof (PcieInitEarlyTable) / sizeof (PCIE_HOST_REGISTER_ENTRY) -}; + ARRAY_SIZE(PcieInitEarlyTable) + }; STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = { { @@ -146,8 +146,8 @@ STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = { CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableKB = { &CoreInitTable[0], - sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY) -}; + ARRAY_SIZE(CoreInitTable) + }; STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = { @@ -197,8 +197,8 @@ STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = { CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableKB = { &PortInitEarlyTable[0], - sizeof (PortInitEarlyTable) / sizeof (PCIE_PORT_REGISTER_ENTRY) -}; + ARRAY_SIZE(PortInitEarlyTable) + }; STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = { @@ -221,5 +221,5 @@ STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = { CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableKB = { &PortInitMidTable[0], - sizeof (PortInitMidTable) / sizeof (PCIE_PORT_REGISTER_ENTRY) -}; + ARRAY_SIZE(PortInitMidTable) + }; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c index 64e7cb36fc..8c25a8b098 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c @@ -139,7 +139,7 @@ PcieAspmBlackListFeature ( GnbLibPciRead (LinkAspm->UpstreamPort.AddressValue, AccessWidth32, &UpstreamDeviceId, StdHeader); GnbLibPciRead (LinkAspm->DownstreamPort.AddressValue, AccessWidth32, &DownstreamDeviceId, StdHeader); LinkAspm->BlackList = FALSE; - for (i = 0; i < (sizeof (AspmBrDeviceTable) / sizeof (UINT16)); i = i + 3) { + for (i = 0; i < ARRAY_SIZE(AspmBrDeviceTable); i = i + 3) { VendorId = AspmBrDeviceTable[i]; DeviceId = AspmBrDeviceTable[i + 1]; if (VendorId == (UINT16)UpstreamDeviceId || VendorId == (UINT16)DownstreamDeviceId ) { @@ -157,7 +157,7 @@ PcieAspmBlackListFeature ( GnbLibPciRMW (LinkAspm->UpstreamPort.AddressValue | 0x70C, AccessS3SaveWidth32, 0x0, 0x0F003F01, StdHeader); DeviceId = UpstreamDeviceId >> 16; - for (i = 0; i < (sizeof (Aspm168cL0sEnabled) / sizeof (UINT16)); i++) { + for (i = 0; i < ARRAY_SIZE(Aspm168cL0sEnabled); i++) { if (DeviceId == Aspm168cL0sEnabled[i]) { LinkAspm->UpstreamAspm = LinkAspm->RequestedAspm & AspmL0sL1; LinkAspm->DownstreamAspm = LinkAspm->UpstreamAspm & AspmL1; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c index edf877264b..a74fe043b7 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c @@ -289,7 +289,7 @@ PciePayloadBlackListFeature ( UINT32 VendorId; GnbLibPciRead (Device.AddressValue, AccessWidth32, &TargetDeviceId, StdHeader); - for (i = 0; i < (sizeof (PayloadBlacklistDeviceTable) / sizeof (UINT16)); i = i + 3) { + for (i = 0; i < ARRAY_SIZE(PayloadBlacklistDeviceTable); i = i + 3) { VendorId = PayloadBlacklistDeviceTable[i]; DeviceId = PayloadBlacklistDeviceTable[i + 1]; if (VendorId == (UINT16)TargetDeviceId) { diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c index 6ca3859b8e..95a464ae82 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c @@ -242,7 +242,7 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorKB[] = { CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefKB = { 0, - (sizeof (S3PciPreSelfRefDescriptorKB) / sizeof (PCI_REG_DESCRIPTOR)), + ARRAY_SIZE(S3PciPreSelfRefDescriptorKB), S3PciPreSelfRefDescriptorKB, PciSpecialCaseFuncKB }; @@ -414,7 +414,7 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorKB[] = { CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefKB = { 0, - (sizeof (S3CPciPreSelfDescriptorKB) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + ARRAY_SIZE(S3CPciPreSelfDescriptorKB), S3CPciPreSelfDescriptorKB, PciSpecialCaseFuncKB }; @@ -608,7 +608,7 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = { CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefKB = { 0, - (sizeof (S3CPciPostSelfDescriptorKB) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + ARRAY_SIZE(S3CPciPostSelfDescriptorKB), S3CPciPostSelfDescriptorKB, PciSpecialCaseFuncKB }; @@ -638,7 +638,7 @@ MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorKB[] = { CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefKB = { 0, - (sizeof (S3MSRPreSelfRefDescriptorKB) / sizeof (MSR_REG_DESCRIPTOR)), + ARRAY_SIZE(S3MSRPreSelfRefDescriptorKB), S3MSRPreSelfRefDescriptorKB, MsrSpecialCaseFuncKB }; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c index 113386e20b..f632337a3b 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c @@ -207,12 +207,12 @@ MemConstructTechBlock3 ( // // Initialize the SPD pointers for each Dimm // - for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) { + for (i = 0 ; i < ARRAY_SIZE(ChannelPtr->DimmSpdPtr); i++) { ChannelPtr->DimmSpdPtr[i] = NULL; } for (i = 0 ; i < DimmSlots; i++) { ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]); - if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) { + if ( (i + 2) < ARRAY_SIZE(ChannelPtr->DimmSpdPtr)) { if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) { if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_RANKS] >> 3) & 0x07) + 1) > 2) { ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]); diff --git a/src/vendorcode/amd/cimx/sb900/SBPort.c b/src/vendorcode/amd/cimx/sb900/SBPort.c index 90e878e1a6..75df24655c 100644 --- a/src/vendorcode/amd/cimx/sb900/SBPort.c +++ b/src/vendorcode/amd/cimx/sb900/SBPort.c @@ -330,7 +330,8 @@ sbPowerOnInit ( // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14)); // } //Program power on pci init table - programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) ); + programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), + ARRAY_SIZE(sbPorInitPciTable)); programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr)); diff --git a/src/vendorcode/amd/cimx/sb900/Sata.c b/src/vendorcode/amd/cimx/sb900/Sata.c index 9d1655c164..397ed7d0ab 100644 --- a/src/vendorcode/amd/cimx/sb900/Sata.c +++ b/src/vendorcode/amd/cimx/sb900/Sata.c @@ -487,7 +487,7 @@ sataInitBeforePciEnum ( // RPR 9.5 SATA PHY Programming Sequence pPhyTable = (SATAPHYSETTING*)FIXUP_PTR (&sataPhyTable[0]); - for (i = 0; i < (sizeof (sataPhyTable) / sizeof (SATAPHYSETTING)); i++) { + for (i = 0; i < ARRAY_SIZE(sataPhyTable); i++) { RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG80, AccWidthUint16 | S3_SAVE, 0x00, pPhyTable->wPhyCoreControl); RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG98, AccWidthUint32 | S3_SAVE, 0x00, pPhyTable->dwPhyFineTune); ++pPhyTable; diff --git a/src/vendorcode/amd/cimx/sb900/SbCmn.c b/src/vendorcode/amd/cimx/sb900/SbCmn.c index 1767ea1f24..b1784d7ddd 100644 --- a/src/vendorcode/amd/cimx/sb900/SbCmn.c +++ b/src/vendorcode/amd/cimx/sb900/SbCmn.c @@ -397,7 +397,8 @@ commonInitEarlyBoot ( //Make BAR registers of smbus visible. RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0); //Early post initialization of pci config space - programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) ); + programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), + ARRAY_SIZE(sbEarlyPostByteInitTable)); if ( pConfig->BuildParameters.SmbusSsid != 0 ) { RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid); } diff --git a/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c b/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c index 9304e78d60..fdca040cb3 100644 --- a/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c +++ b/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c @@ -134,7 +134,7 @@ void __bdk_dram_flush_to_mem_range(uint64_t area, uint64_t max_address) */ const char *bdk_dram_get_test_name(int test) { - if (test < (int)(sizeof(TEST_INFO) / sizeof(TEST_INFO[0]))) + if (test < (int) ARRAY_SIZE(TEST_INFO)) return TEST_INFO[test].name; else return NULL; diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-xfi.c b/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-xfi.c index 77ba4c4233..c0dee6cabe 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-xfi.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-xfi.c @@ -141,7 +141,7 @@ int bdk_xfi_vsc7224_dump(int twsi_id, int unit){ uint64_t pagenum[9] = {0x00, 0x01, 0x02, 0x03, 0x20, 0x21, 0x30, 0x31, 0x40}; - for(p=0; p < (sizeof(pagenum)/sizeof(pagenum[0])); p++){ + for(p=0; p < ARRAY_SIZE(pagenum); p++){ data = pagenum[p]; bdk_twsix_write_ia(node, twsi_id, dev_addr, internal_addr, num_bytes, ia_width_bytes, data); for(i=0x80; i<=0xFF; i++){ diff --git a/src/vendorcode/cavium/bdk/libdram/libdram-config-load.c b/src/vendorcode/cavium/bdk/libdram/libdram-config-load.c index 76b5ddc57d..a16954e8b0 100644 --- a/src/vendorcode/cavium/bdk/libdram/libdram-config-load.c +++ b/src/vendorcode/cavium/bdk/libdram/libdram-config-load.c @@ -147,7 +147,7 @@ static void load_rank_data(dram_config_t *cfg, int ranks, int num_dimms, int lmc const dram_config_t *libdram_config_load(bdk_node_t node) { dram_config_t *cfg = &__libdram_global_cfg; - const int MAX_LMCS = sizeof(cfg->config) / sizeof(cfg->config[0]); + const int MAX_LMCS = ARRAY_SIZE(cfg->config); /* Make all fields for the node default to zero */ memset(cfg, 0, sizeof(*cfg)); |