diff options
| author | Changqi Hu <changqi.hu@mediatek.com> | 2019-08-23 12:01:30 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-06 15:30:43 +0000 |
| commit | 6b2a54030fe1821a9e7360d3da668e1a710fada0 (patch) | |
| tree | 2e7d44a6213e8bff0d4dba8a934333ecf7d8640e | |
| parent | 1b439d9ceddb1ee7383c4cc69b272fc70acb3810 (diff) | |
soc/mediatek: Fix USB enumeration issue
Some USB 3.0 devices fail to be enumerated after USB reset, and xhci
port status register shows the device is disconnected. After measuring
the USB signal, we found that the USB disconnect threshold was lower and
that the disconnect event was triggered unexpectedly.
USB designers suggest changing discth to 15.
BUG=b:122047652
TEST=emerge-kukui coreboot chromeos-bootimage
Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1
Signed-off-by: Changqi Hu <changqi.hu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
| -rw-r--r-- | src/soc/mediatek/common/include/soc/usb_common.h | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/common/usb.c | 4 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h index 8a36c6a66b..22704e77b5 100644 --- a/src/soc/mediatek/common/include/soc/usb_common.h +++ b/src/soc/mediatek/common/include/soc/usb_common.h @@ -70,6 +70,8 @@ struct ssusb_ippc_regs { #define PA6_RG_U2_ISO_EN (0x1 << 31) #define PA6_RG_U2_BC11_SW_EN (0x1 << 23) #define PA6_RG_U2_OTG_VBUSCMP_EN (0x1 << 20) +#define PA6_RG_U2_DISCTH (0xf << 4) +#define PA6_RG_U2_DISCTH_VAL(x) ((0xf & (x)) << 4) #define PA6_RG_U2_SQTH (0xf << 0) #define PA6_RG_U2_SQTH_VAL(x) ((0xf & (x)) << 0) diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c index dcb93073b7..328bf66e0f 100644 --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -76,6 +76,10 @@ static void phy_index_power_on(int index) /* Set USB 2.0 slew rate value */ clrsetbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4)); + + /* Set USB 2.0 disconnect threshold */ + clrsetbits_le32(&phy->u2phy.usbphyacr6, + PA6_RG_U2_DISCTH, PA6_RG_U2_DISCTH_VAL(15)); } static void u3phy_power_on(void) |