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authorFelix Held <felix-coreboot@felixheld.de>2022-05-06 17:50:07 +0200
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-05-12 18:44:11 +0000
commit68aaa8cc26026225179547c44dfb39d8ac775da4 (patch)
tree4e7f8bb8a76e874a5e9ad03c78d89258101b09da
parent3dc89c5bd73ad1e236952f27421678e7fef24225 (diff)
soc/amd/sabrina/fsp_m_params: don't hard-code USB PHY config table size
Use sizeof instead of having a hard-coded struct length. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3c39d770a7719e30572e71b6a6c24fa2ad4a9426 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
-rw-r--r--src/soc/amd/sabrina/fsp_m_params.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/amd/sabrina/fsp_m_params.c b/src/soc/amd/sabrina/fsp_m_params.c
index 8a8300841d..d319c3420f 100644
--- a/src/soc/amd/sabrina/fsp_m_params.c
+++ b/src/soc/amd/sabrina/fsp_m_params.c
@@ -13,6 +13,7 @@
#include <soc/pci_devs.h>
#include <string.h>
#include <types.h>
+#include <vendorcode/amd/fsp/sabrina/FspUsb.h>
#include "chip.h"
__weak void mb_pre_fspm(void)
@@ -145,7 +146,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mcfg->usb_phy = (struct usb_phy_config *)&config->usb_phy;
mcfg->usb_phy->Version_Major = 0xd;
mcfg->usb_phy->Version_Minor = 0x6;
- mcfg->usb_phy->TableLength = 100;
+ mcfg->usb_phy->TableLength = sizeof(struct usb_phy_config);
} else {
mcfg->usb_phy = NULL;
}