mrc_cache: Move code for triggering memory training into mrc_cache

Currently the decision of whether or not to use mrc_cache in recovery
mode is made within the individual platforms' drivers (ie: fsp2.0,
fsp1.1, etc.).  As this is not platform specific, but uses common
vboot infrastructure, the code can be unified and moved into
mrc_cache.  The conditions are as follows:

  1.  If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain
      switch is true)
  2.  If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this
      means that memory training will occur after verified boot,
      meaning that mrc_cache will be filled with data from executing
      RW code.  So in this case, we never want to use the training
      data in the mrc_cache for recovery mode.
  3.  If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this
      means that memory training happens before verfied boot, meaning
      that the mrc_cache data is generated by RO code, so it is safe
      to use for a recovery boot.
  4.  Any platform that does not use vboot should be unaffected.

Additionally, we have removed the
MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the
mrc_cache driver takes care of invalidating the mrc_cache data for
normal mode.  If the platform:
  1.  !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data
  2.  HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set

BUG=b:150502246
BRANCH=None
TEST=1. run dut-control power_state:rec_force_mrc twice on lazor
        ensure that memory retraining happens both times
        run dut-control power_state:rec twice on lazor
        ensure that memory retraining happens only first time
     2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig
        boot twice to ensure caching of memory training occurred
	on each boot.

Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

23 files changed, 103 insertions, 105 deletions

diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 5a59c502a9..5129dc696b 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -41,35 +41,29 @@ static void raminit_common(struct romstage_params *params)
 	params->saved_data_size = 0;
 	params->saved_data = NULL;
 	if (!params->disable_saved_data) {
-		if (vboot_recovery_mode_enabled()) {
-			/* Recovery mode does not use MRC cache */
+		/* Assume boot device is memory mapped. */
+		assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
+
+		params->saved_data = NULL;
+		if (CONFIG(CACHE_MRC_SETTINGS))
+			params->saved_data =
+				mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
+							    params->fsp_version,
+							    &mrc_size);
+		if (params->saved_data) {
+			/* MRC cache found */
+			params->saved_data_size = mrc_size;
+
+		} else if (s3wake) {
+			/* Waking from S3 and no cache. */
 			printk(BIOS_DEBUG,
-			       "Recovery mode: not using MRC cache.\n");
+			       "No MRC cache "
+			       "found in S3 resume path.\n");
+			post_code(POST_RESUME_FAILURE);
+			/* FIXME: A "system" reset is likely enough: */
+			full_reset();
 		} else {
-			/* Assume boot device is memory mapped. */
-			assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
-
-			params->saved_data = NULL;
-			if (CONFIG(CACHE_MRC_SETTINGS))
-				params->saved_data =
-					mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
-								    params->fsp_version,
-								    &mrc_size);
-			if (params->saved_data) {
-				/* MRC cache found */
-				params->saved_data_size = mrc_size;
-
-			} else if (s3wake) {
-				/* Waking from S3 and no cache. */
-				printk(BIOS_DEBUG,
-				       "No MRC cache "
-				       "found in S3 resume path.\n");
-				post_code(POST_RESUME_FAILURE);
-				/* FIXME: A "system" reset is likely enough: */
-				full_reset();
-			} else {
-				printk(BIOS_DEBUG, "No MRC cache found.\n");
-			}
+			printk(BIOS_DEBUG, "No MRC cache found.\n");
 		}
 	}
 
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 68cc1215a5..27e34fef0d 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -92,18 +92,6 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version)
 	if (!CONFIG(CACHE_MRC_SETTINGS))
 		return;
 
-	/*
-	 * In recovery mode, force retraining:
-	 * 1. Recovery cache is not supported, or
-	 * 2. Memory retrain switch is set.
-	 */
-	if (vboot_recovery_mode_enabled()) {
-		if (!CONFIG(HAS_RECOVERY_MRC_CACHE))
-			return;
-		if (get_recovery_mode_retrain_switch())
-			return;
-	}
-
 	/* Assume boot device is memory mapped. */
 	assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
 
diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig
index b09c19672e..df6973b0a4 100644
--- a/src/drivers/mrc_cache/Kconfig
+++ b/src/drivers/mrc_cache/Kconfig
@@ -17,11 +17,6 @@ config HAS_RECOVERY_MRC_CACHE
 	bool
 	default n
 
-config MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
-	bool
-	depends on VBOOT_STARTS_IN_BOOTBLOCK
-	default n
-
 config MRC_SETTINGS_VARIABLE_DATA
 	bool
 	default n
diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c
index eb43123c67..8b26ea5905 100644
--- a/src/drivers/mrc_cache/mrc_cache.c
+++ b/src/drivers/mrc_cache/mrc_cache.c
@@ -69,7 +69,20 @@ static const struct cache_region normal_training = {
 	.type = MRC_TRAINING_DATA,
 	.elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL,
 	.tpm_hash_index = MRC_RW_HASH_NV_INDEX,
+#if CONFIG(VBOOT_STARTS_IN_ROMSTAGE)
+	/*
+	 * If VBOOT_STARTS_IN_ROMSTAGE is selected, this means that
+	 * memory training happens before vboot (in RO) and the
+	 * mrc_cache data is always safe to use.
+	 */
 	.flags = NORMAL_FLAG | RECOVERY_FLAG,
+#else
+	/*
+	 * If !VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens after
+	 * vboot (in RW code) and is never safe to use in recovery.
+	 */
+	.flags = NORMAL_FLAG,
+#endif
 };
 
 static const struct cache_region variable_data = {
@@ -78,7 +91,20 @@ static const struct cache_region variable_data = {
 	.type = MRC_VARIABLE_DATA,
 	.elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE,
 	.tpm_hash_index = 0,
+#if CONFIG(VBOOT_STARTS_IN_ROMSTAGE)
+	/*
+	 * If VBOOT_STARTS_IN_ROMSTAGE is selected, this means that
+	 * memory training happens before vboot (in RO) and the
+	 * mrc_cache data is always safe to use.
+	 */
 	.flags = NORMAL_FLAG | RECOVERY_FLAG,
+#else
+	/*
+	 * If !VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens after
+	 * vboot (in RW code) and is never safe to use in recovery.
+	 */
+	.flags = NORMAL_FLAG,
+#endif
 };
 
 /* Order matters here for priority in matching. */
@@ -255,6 +281,13 @@ static int mrc_cache_find_current(int type, uint32_t version,
 	const size_t md_size = sizeof(*md);
 	const bool fail_bad_data = true;
 
+	/*
+	 * In recovery mode, force retraining if the memory retrain
+	 * switch is set.
+	 */
+	if (vboot_recovery_mode_enabled() && get_recovery_mode_retrain_switch())
+		return -1;
+
 	cr = lookup_region(&region, type);
 
 	if (cr == NULL)
@@ -566,10 +599,24 @@ static void invalidate_normal_cache(void)
 	const char *name = DEFAULT_MRC_CACHE;
 	const uint32_t invalid = ~MRC_DATA_SIGNATURE;
 
-	/* Invalidate only on recovery mode with retraining enabled. */
+	/*
+	 * If !HAS_RECOVERY_MRC_CACHE and VBOOT_STARTS_IN_ROMSTAGE is
+	 * selected, this means that memory training occurs before
+	 * verified boot (in RO), so normal mode cache does not need
+	 * to be invalidated.
+	 */
+	if (!CONFIG(HAS_RECOVERY_MRC_CACHE) && CONFIG(VBOOT_STARTS_IN_ROMSTAGE))
+		return;
+
+	/* We only invalidate the normal cache in recovery mode. */
 	if (!vboot_recovery_mode_enabled())
 		return;
-	if (!get_recovery_mode_retrain_switch())
+
+	/*
+	 * For platforms with a recovery mrc_cache, no need to
+	 * invalidate when retrain switch is not set.
+	 */
+	if (CONFIG(HAS_RECOVERY_MRC_CACHE) && !get_recovery_mode_retrain_switch())
 		return;
 
 	if (fmap_locate_area_as_rdev_rw(name, &rdev) < 0) {
@@ -599,7 +646,7 @@ static void update_mrc_cache_from_cbmem(int type)
 	cr = lookup_region(&region, type);
 
 	if (cr == NULL) {
-		printk(BIOS_ERR, "MRC: could not find cache_region type %d\n", type);
+		printk(BIOS_INFO, "MRC: could not find cache_region type %d\n", type);
 		return;
 	}
 
@@ -631,8 +678,7 @@ static void finalize_mrc_cache(void *unused)
 			update_mrc_cache_from_cbmem(MRC_VARIABLE_DATA);
 	}
 
-	if (CONFIG(MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN))
-		invalidate_normal_cache();
+	invalidate_normal_cache();
 
 	protect_mrc_region();
 }
@@ -642,13 +688,6 @@ int mrc_cache_stash_data(int type, uint32_t version, const void *data,
 {
 	const struct cache_region *cr;
 
-	cr = lookup_region_type(type);
-	if (cr == NULL) {
-		printk(BIOS_ERR, "MRC: failed to add to cbmem for type %d.\n",
-			type);
-		return -1;
-	}
-
 	struct mrc_metadata md = {
 		.signature = MRC_DATA_SIGNATURE,
 		.data_size = size,
@@ -664,6 +703,13 @@ int mrc_cache_stash_data(int type, uint32_t version, const void *data,
 		size_t cbmem_size;
 		cbmem_size = sizeof(*cbmem_md) + size;
 
+		cr = lookup_region_type(type);
+		if (cr == NULL) {
+			printk(BIOS_INFO, "MRC: No region type found. Skip adding to cbmem for type %d.\n",
+				type);
+			return 0;
+		}
+
 		cbmem_md = cbmem_add(cr->cbmem_id, cbmem_size);
 
 		if (cbmem_md == NULL) {
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 6da65052cd..891b48acc9 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -47,7 +47,6 @@ config CHROMEOS
 	select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
 	select GBB_FLAG_FORCE_MANUAL_RECOVERY
 	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 	select VBOOT_EARLY_EC_SYNC
 	select VBOOT_LID_SWITCH
 
diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig
index dafd593ab6..8d958493bd 100644
--- a/src/mainboard/google/deltaur/Kconfig
+++ b/src/mainboard/google/deltaur/Kconfig
@@ -90,7 +90,6 @@ config VARIANT_DIR
 
 config VBOOT
 	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 	select VBOOT_LID_SWITCH
 
 endif # BOARD_GOOGLE_BASEBOARD_DELTAUR
diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig
index d535d141e1..6c90eed9a8 100644
--- a/src/mainboard/google/drallion/Kconfig
+++ b/src/mainboard/google/drallion/Kconfig
@@ -93,7 +93,6 @@ config DEVICETREE
 
 config VBOOT
 	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 	select VBOOT_LID_SWITCH
 
 endif # BOARD_GOOGLE_BASEBOARD_DRALLION
diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig
index 9316c7f213..ece0119a3e 100644
--- a/src/mainboard/google/eve/Kconfig
+++ b/src/mainboard/google/eve/Kconfig
@@ -28,7 +28,6 @@ config VBOOT
 	select EC_GOOGLE_CHROMEEC_SWITCHES
 	select HAS_RECOVERY_MRC_CACHE
 	select VBOOT_LID_SWITCH
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 
 config CHROMEOS
 	select DSAR_ENABLE
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index a21df378ef..e09f853337 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -40,7 +40,6 @@ config OVERRIDE_DEVICETREE
 config VBOOT
 	select EC_GOOGLE_CHROMEEC_SWITCHES
 	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 
 config DRIVER_TPM_SPI_BUS
 	default 0x1
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 4d7d5ec990..12e56384bd 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -54,7 +54,6 @@ config CHROMEOS
 	select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
 	select GBB_FLAG_FORCE_MANUAL_RECOVERY
 	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 	select VBOOT_LID_SWITCH
 	select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU
 
@@ -183,7 +182,6 @@ config VARIANT_DIR
 
 config VBOOT
 	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 	select VBOOT_EARLY_EC_SYNC
 
 config USE_PM_ACPI_TIMER
diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index b9c6a1ba34..588c8ed331 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -46,7 +46,6 @@ config CHROMEOS
 	default y
 	select EC_GOOGLE_CHROMEEC_SWITCHES
 	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 	select VBOOT_LID_SWITCH
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig
index d8b90bcdc3..2656d28173 100644
--- a/src/mainboard/google/poppy/Kconfig
+++ b/src/mainboard/google/poppy/Kconfig
@@ -208,7 +208,6 @@ config VARIANT_SPECIFIC_OPTIONS_SORAKA
 config VBOOT
 	select EC_GOOGLE_CHROMEEC_SWITCHES
 	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 	select VBOOT_LID_SWITCH
 
 config UART_FOR_CONSOLE
diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index 76a864062f..9744d74738 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -43,7 +43,6 @@ config TPM_TIS_ACPI_INTERRUPT
 config VBOOT
 	select EC_GOOGLE_CHROMEEC_SWITCHES
 	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 	select VBOOT_LID_SWITCH if BASEBOARD_REEF_LAPTOP
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig
index 5b580724bb..9b0d25158c 100644
--- a/src/mainboard/google/sarien/Kconfig
+++ b/src/mainboard/google/sarien/Kconfig
@@ -94,7 +94,6 @@ config DEVICETREE
 
 config VBOOT
 	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 	select VBOOT_LID_SWITCH
 
 endif # BOARD_GOOGLE_BASEBOARD_SARIEN
diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index a5cc1966dc..07a5fde7a1 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -45,7 +45,6 @@ config CHROMEOS
 	select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
 	select GBB_FLAG_FORCE_MANUAL_RECOVERY
 	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 	select VBOOT_LID_SWITCH
 	select VBOOT_EARLY_EC_SYNC
 
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig
index 57b0524ce3..b6d3ff3cdb 100644
--- a/src/mainboard/intel/adlrvp/Kconfig
+++ b/src/mainboard/intel/adlrvp/Kconfig
@@ -25,7 +25,6 @@ config CHROMEOS
 	select GBB_FLAG_FORCE_MANUAL_RECOVERY
 	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
 	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 
 config MAINBOARD_DIR
 	string
@@ -82,7 +81,6 @@ config VBOOT
 	select VBOOT_LID_SWITCH
 	select VBOOT_MOCK_SECDATA
 	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 
 config UART_FOR_CONSOLE
 	int
diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig
index 7b1b564e52..172dfa2e97 100644
--- a/src/mainboard/intel/glkrvp/Kconfig
+++ b/src/mainboard/intel/glkrvp/Kconfig
@@ -45,7 +45,6 @@ config CHROMEOS
 
 config VBOOT
 	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 	select EC_GOOGLE_CHROMEEC_SWITCHES if GLK_CHROME_EC
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig
index 1125a9b7f2..7bfd15878c 100644
--- a/src/mainboard/intel/jasperlake_rvp/Kconfig
+++ b/src/mainboard/intel/jasperlake_rvp/Kconfig
@@ -59,7 +59,6 @@ config CHROMEOS
 	select GBB_FLAG_FORCE_MANUAL_RECOVERY
 	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
 	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 
 config VBOOT
 	select VBOOT_LID_SWITCH
diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig
index 4d43e23454..9df542dfa6 100644
--- a/src/mainboard/intel/tglrvp/Kconfig
+++ b/src/mainboard/intel/tglrvp/Kconfig
@@ -31,7 +31,6 @@ config CHROMEOS
 	select EC_GOOGLE_CHROMEEC_SWITCHES if TGL_CHROME_EC
 	select GBB_FLAG_FORCE_MANUAL_RECOVERY
 	select HAS_RECOVERY_MRC_CACHE
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 	select GBB_FLAG_FORCE_DEV_SWITCH_ON
 	select GBB_FLAG_FORCE_DEV_BOOT_USB
 	select VBOOT_EARLY_EC_SYNC
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 63d70f792f..290e402fcb 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -112,10 +112,11 @@ void sdram_initialize(struct pei_data *pei_data)
 
 	printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n");
 
-	/* Do not pass MRC data in for recovery mode boot, always pass it in for S3 resume */
-	if (!(CONFIG(HASWELL_VBOOT_IN_BOOTBLOCK) && vboot_recovery_mode_enabled())
-	    || pei_data->boot_mode == 2)
-		prepare_mrc_cache(pei_data);
+	/*
+	 * Always pass in mrc_cache data.  The driver will determine
+	 * whether to use the data or not.
+	 */
+	prepare_mrc_cache(pei_data);
 
 	/* If MRC data is not found, we cannot continue S3 resume */
 	if (pei_data->boot_mode == 2 && !pei_data->mrc_input) {
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 444ecf8cc7..8df7d1b36a 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -133,12 +133,10 @@ void sdram_initialize(struct pei_data *pei_data)
 	printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n");
 
 	/*
-	 * Do not pass MRC data in for recovery mode boot,
-	 * Always pass it in for S3 resume.
+	 * Always pass in mrc_cache data.  The driver will determine
+	 * whether to use the data or not.
 	 */
-	if (!(CONFIG(SANDYBRIDGE_VBOOT_IN_BOOTBLOCK) && vboot_recovery_mode_enabled()) ||
-	    pei_data->boot_mode == 2)
-		prepare_mrc_cache(pei_data);
+	prepare_mrc_cache(pei_data);
 
 	/* If MRC data is not found we cannot continue S3 resume. */
 	if (pei_data->boot_mode == 2 && !pei_data->mrc_input) {
diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c
index 7020ddfe0d..e51b4f7b66 100644
--- a/src/soc/intel/broadwell/raminit.c
+++ b/src/soc/intel/broadwell/raminit.c
@@ -85,29 +85,23 @@ void raminit(struct pei_data *pei_data)
 
 	broadwell_fill_pei_data(pei_data);
 
-	if (CONFIG(BROADWELL_VBOOT_IN_BOOTBLOCK) &&
-	    vboot_recovery_mode_enabled()) {
-		/* Recovery mode does not use MRC cache */
-		printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n");
+	/* Assume boot device is memory mapped. */
+	assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
+
+	pei_data->saved_data =
+		mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0,
+					    &mrc_size);
+	if (pei_data->saved_data) {
+		/* MRC cache found */
+		pei_data->saved_data_size = mrc_size;
+	} else if (pei_data->boot_mode == ACPI_S3) {
+		/* Waking from S3 and no cache. */
+		printk(BIOS_DEBUG,
+		       "No MRC cache found in S3 resume path.\n");
+		post_code(POST_RESUME_FAILURE);
+		system_reset();
 	} else {
-		/* Assume boot device is memory mapped. */
-		assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
-
-		pei_data->saved_data =
-			mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0,
-						    &mrc_size);
-		if (pei_data->saved_data) {
-			/* MRC cache found */
-			pei_data->saved_data_size = mrc_size;
-		} else if (pei_data->boot_mode == ACPI_S3) {
-			/* Waking from S3 and no cache. */
-			printk(BIOS_DEBUG,
-			       "No MRC cache found in S3 resume path.\n");
-			post_code(POST_RESUME_FAILURE);
-			system_reset();
-		} else {
-			printk(BIOS_DEBUG, "No MRC cache found.\n");
-		}
+		printk(BIOS_DEBUG, "No MRC cache found.\n");
 	}
 
 	/*
diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig
index 4cd1c41cac..066ff5db1c 100644
--- a/src/soc/qualcomm/sc7180/Kconfig
+++ b/src/soc/qualcomm/sc7180/Kconfig
@@ -33,7 +33,6 @@ config VBOOT
 	select VBOOT_RETURN_FROM_VERSTAGE
 	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_STARTS_IN_BOOTBLOCK
-	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 
 config SC7180_QSPI
 	bool