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authorFelix Held <felix-coreboot@felixheld.de>2022-03-30 19:39:06 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-04-01 14:32:53 +0000
commit65c0655881752ddf551b44e3c3261605e74081e5 (patch)
tree2fe156400cd41b450265d765d7feee54d5faa2df
parented32977a39711656f776f8b8917ae2d63e13e1cc (diff)
soc/amd/sabrina/makefile: drop multilevel option in amdfwtool calls
Since Sabrina uses the image slot header (ISH) that depends on the AMD A/B recovery scheme that depends on the multi-level PSP directory support, the multi-level support gets automatically selected by passing Sabrina as SoC name to amdfwtool, so passing the --multilevel command line switch to amdfwtool isn't needed. TEST=Timeless build results in identical binary for chausie Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I98154d5b47daca6ae7952ffd3175d98ea3e01845 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
-rw-r--r--src/soc/amd/sabrina/Makefile.inc3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/amd/sabrina/Makefile.inc b/src/soc/amd/sabrina/Makefile.inc
index b5045899d0..b7b538e193 100644
--- a/src/soc/amd/sabrina/Makefile.inc
+++ b/src/soc/amd/sabrina/Makefile.inc
@@ -232,7 +232,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
$(OPT_VERSTAGE_FILE) \
$(OPT_VERSTAGE_SIG_FILE) \
--location $(shell printf "%#x" $(SABRINA_FWM_POSITION)) \
- --multilevel \
--output $@
$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
@@ -250,7 +249,6 @@ $(obj)/amdfw_a.rom: $(obj)/amdfw.rom
$(OPT_APOB_NV_BASE) \
--location $(shell printf "%#x" $(SABRINA_FW_A_POSITION)) \
--anywhere \
- --multilevel \
--output $@
$(obj)/amdfw_b.rom: $(obj)/amdfw.rom
@@ -262,7 +260,6 @@ $(obj)/amdfw_b.rom: $(obj)/amdfw.rom
$(OPT_APOB_NV_BASE) \
--location $(shell printf "%#x" $(SABRINA_FW_B_POSITION)) \
--anywhere \
- --multilevel \
--output $@