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authorBora Guvendik <bora.guvendik@intel.com>2017-05-08 16:29:17 -0700
committerAaron Durbin <adurbin@chromium.org>2017-06-16 17:37:06 +0200
commit65623b7264eed9c9e6e1a976983708bbf3bd5b79 (patch)
treedd11bce4f4cb28ccc11fe05bf4d37f808718fe86
parent94ee328b97a7bf03fa8c80474cce434a2ff43bbd (diff)
soc/intel/apollolake: Use SCS common code
This patch uses common SCS library to setup sd card. Change-Id: Iafbba04d7a498b9a321e8efee4abf07820d17330 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/19632 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
-rw-r--r--src/soc/intel/apollolake/Kconfig2
-rw-r--r--src/soc/intel/apollolake/sd.c81
2 files changed, 16 insertions, 67 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index deb510eda3..8d9f56293a 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -61,9 +61,9 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_I2C
select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_PCR
- select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
+ select SOC_INTEL_COMMON_BLOCK_SCS
select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_XDCI
diff --git a/src/soc/intel/apollolake/sd.c b/src/soc/intel/apollolake/sd.c
index e2b5ab4fbe..35db8040a0 100644
--- a/src/soc/intel/apollolake/sd.c
+++ b/src/soc/intel/apollolake/sd.c
@@ -13,76 +13,25 @@
* GNU General Public License for more details.
*/
-#include <arch/acpi_device.h>
-#include <arch/acpigen.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <gpio.h>
+#include <intelblocks/sd.h>
#include "chip.h"
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
-static void sd_fill_ssdt(struct device *dev)
+int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev)
{
config_t *config = dev->chip_info;
- const char *path;
- struct acpi_gpio default_gpio = {
- .type = ACPI_GPIO_TYPE_INTERRUPT,
- .pull = ACPI_GPIO_PULL_NONE,
- .irq.mode = ACPI_IRQ_EDGE_TRIGGERED,
- .irq.polarity = ACPI_IRQ_ACTIVE_BOTH,
- .irq.shared = ACPI_IRQ_SHARED,
- .irq.wake = ACPI_IRQ_WAKE,
- .interrupt_debounce_timeout = 10000, /* 100ms */
- .pin_count = 1,
- .pins = { config->sdcard_cd_gpio }
- };
- struct acpi_dp *dp;
- if (!dev->enabled)
- return;
-
- /* Use device path as the Scope for the SSDT */
- path = acpi_device_path(dev);
- if (!path)
- return;
if (!config->sdcard_cd_gpio)
- return;
- acpigen_write_scope(path);
- acpigen_write_name("_CRS");
-
- /* Write GpioInt() as default (if set) or custom from devicetree */
- acpigen_write_resourcetemplate_header();
- acpi_device_write_gpio(&default_gpio);
- acpigen_write_resourcetemplate_footer();
-
- /* Bind the cd-gpio name to the GpioInt() resource */
- dp = acpi_dp_new_table("_DSD");
- acpi_dp_add_gpio(dp, "cd-gpio", path, 0, 0, 1);
- acpi_dp_write(dp);
-
- acpigen_pop_len();
+ return -1;
+
+ gpio->type = ACPI_GPIO_TYPE_INTERRUPT;
+ gpio->pull = ACPI_GPIO_PULL_NONE;
+ gpio->irq.mode = ACPI_IRQ_EDGE_TRIGGERED;
+ gpio->irq.polarity = ACPI_IRQ_ACTIVE_BOTH;
+ gpio->irq.shared = ACPI_IRQ_SHARED;
+ gpio->irq.wake = ACPI_IRQ_WAKE;
+ gpio->interrupt_debounce_timeout = 10000; /* 100ms */
+ gpio->pin_count = 1;
+ gpio->pins[0] = config->sdcard_cd_gpio;
+
+ return 0;
}
-#endif
-
-static struct device_operations dev_ops = {
- .read_resources = &pci_dev_read_resources,
- .set_resources = &pci_dev_set_resources,
- .enable_resources = &pci_dev_enable_resources,
- .ops_pci = &soc_pci_ops,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
- .acpi_fill_ssdt_generator = &sd_fill_ssdt,
-#endif
-};
-
-static const unsigned short pci_device_ids[] = {
- PCI_DEVICE_ID_INTEL_APL_SD,
- PCI_DEVICE_ID_INTEL_GLK_SD,
- 0,
-};
-
-static const struct pci_driver pch_sd __pci_driver = {
- .ops = &dev_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .devices= pci_device_ids,
-};