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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-05-12 01:17:35 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-12 23:32:46 +0000 |
| commit | 62682e79a72bbc25c5c3ef937b347c8ae32a136c (patch) | |
| tree | 23a5cc0f7ce07ca1fe6a1ac6f6373c5703e801cf | |
| parent | 7216053a4207bd6aebd7250e94d59de5e6563680 (diff) | |
soc/amd/cezanne/chip.h: add DPTC and tablet mode options
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I39218b79a79f1ccaf1a58408c6bb5161acea64aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54073
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/cezanne/chip.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 244f2ba303..e770670e05 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -75,6 +75,14 @@ struct soc_amd_cezanne_config { uint32_t telemetry_vddcrsocfull_scale_current_mA; uint32_t telemetry_vddcrsocoffset; + /* Enable dptc for tablet mode (0 = disable, 1 = enable) */ + uint8_t dptc_enable; + + /* STAPM Configuration for tablet mode (need enable dptc_enable first) */ + uint32_t fast_ppt_limit_tablet_mode_mW; + uint32_t slow_ppt_limit_tablet_mode_mW; + uint32_t sustained_power_limit_tablet_mode_mW; + uint32_t thermctl_limit_tablet_mode_degreeC; }; #endif /* CEZANNE_CHIP_H */ |