diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2016-06-29 07:17:21 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2016-06-30 10:54:51 +0200 |
| commit | 61f4b42f2c1bdf5fb09ad4ba22e8420c6f9fbe00 (patch) | |
| tree | 2b39346495a2cc9b1bfa57d3b0d995f145dfe5c9 | |
| parent | 66c20c4dfa0e84b4998b4125dfe153f9c9e09c13 (diff) | |
fsp_broadwell_de: Enable Super I/O address range decode
If there is an external 16550 like UART, one needs to enable
the appropriate address ranges before console_init() is called
so that the init sequence can reach the external UART. Otherwise
the UART will only start working in ramstage and will produce
unreadable characters in romstage due to the lack of initialization.
Tested-on: Siemens MC_BDX1
Change-Id: Iafc5b5b6df14916c5ed778928521d4a8f539cf46
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15495
Tested-by: build bot (Jenkins)
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/include/soc/lpc.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 7 |
2 files changed, 10 insertions, 1 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h index 2c02ebdf47..0408f7f640 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h @@ -21,6 +21,8 @@ #define REVID 0x08 #define PIRQ_RCR1 0x60 #define PIRQ_RCR2 0x68 +#define LPC_IO_DEC 0x80 +#define LPC_EN 0x82 #define GEN_PMCON_1 0xA0 #define GEN_PMCON_2 0xA2 #define GEN_PMCON_3 0xA4 @@ -83,4 +85,4 @@ #define TCO_TMR_HALT (1 << 11) #define TCO_TMR 0x70 -#endif /* _SOC_LPC_H_ */
\ No newline at end of file +#endif /* _SOC_LPC_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 91c2532af0..309a672710 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -48,6 +48,13 @@ static void init_rtc(void) void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) { post_code(0x40); + if (!IS_ENABLED(CONFIG_INTEGRATED_UART)) { + /* Enable decoding of I/O locations for Super I/O devices */ + pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), + LPC_IO_DEC, 0x0010); + pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), + LPC_EN, 0x340f); + } console_init(); init_rtc(); |