diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2022-10-10 23:01:38 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-12 23:51:09 +0000 |
| commit | 60d9b891f606523d82ca8d9432051b159d28342a (patch) | |
| tree | 325dd40a7df8a98c2208c2896cca35977a735d4c | |
| parent | 6ae4d2e0a6a3cb8a1420cade9367393d121f0008 (diff) | |
soc/intel: Kconfig: Correct UART source clock value in comment
Correct UART source clock value in comment from 120 MHz to 100 MHz.
BUG=b:249530903
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ifc17357051ae0b3bc663da467b4fc809a46024d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68286
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index a73657ee2c..ca0af8a860 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -338,7 +338,7 @@ config VBT_DATA_SIZE_KB # Clock divider parameters for 115200 baud rate # Baudrate = (UART source clock * M) /(N *16) -# ADL UART source clock: 120MHz +# ADL UART source clock: 100MHz config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex default 0x25a diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 468a0baa57..4af32769b6 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -171,7 +171,7 @@ config CONSOLE_UART_BASE_ADDRESS # Clock divider parameters for 115200 baud rate # Baudrate = (UART source clock * M) /(N *16) -# EHL UART source clock: 120MHz +# EHL UART source clock: 100MHz config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex default 0x25a diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 00519d0ecf..67d5bc1b06 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -238,7 +238,7 @@ config VBT_DATA_SIZE_KB # Clock divider parameters for 115200 baud rate # Baudrate = (UART source clock * M) /(N *16) -# MTL UART source clock: 120MHz +# MTL UART source clock: 100MHz config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex default 0x25a diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 7966a87e39..5b09ed706a 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -219,7 +219,7 @@ config CONSOLE_UART_BASE_ADDRESS # Clock divider parameters for 115200 baud rate # Baudrate = (UART source clock * M) /(N *16) -# TGL UART source clock: 120MHz +# TGL UART source clock: 100MHz config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex default 0x25a |