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authorElyes Haouas <ehaouas@noos.fr>2022-10-02 14:34:03 +0200
committerMartin Roth <martin.roth@amd.corp-partner.google.com>2022-10-06 17:02:21 +0000
commit606f4f6c2d2ab4e913bedcd9b2d4ca3c15215778 (patch)
treef6ee192a23f451a937d55ee344db7019f0b0e48f
parent07ad894195c3c5d68eda9f0cbde871166c3d28dc (diff)
sb/intel/common/early_smbus.h: Add <device/pci_type.h>
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Icf459f07948cd29eb251b49fcecefb98c5f5f259 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
-rw-r--r--src/southbridge/intel/common/early_smbus.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/early_smbus.h b/src/southbridge/intel/common/early_smbus.h
index d6a7cbbcce..0dc32c06dc 100644
--- a/src/southbridge/intel/common/early_smbus.h
+++ b/src/southbridge/intel/common/early_smbus.h
@@ -4,6 +4,7 @@
#define SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H
#include <device/pci_def.h>
+#include <device/pci_type.h>
#define PCI_DEV_SMBUS PCI_DEV(0, 0x1f, 3)