nb/intel/haswell/peg: Add PEG driver stub

This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the
Haswell northbridge.  This code is necessary to support the dGPU of the
t440p. Code was cut and pasted from Sandy Bridge with vendor IDs updated
to the correct Haswell values.  Tested on t440p with dGPU on Ubuntu
18.04.4 with 5.3.0-28 kernel. Without patches dmesg reports Nouveau is
unable to read the VBIOS of the dGPU as it has an invalid checksum (I
checked that the ROM in CBFS is correct). With this patch DRM works
correctly with both the Nouveau driver and the Nvidia proprietary
driver. Windows 10 1909 also tested but generates bluescreen once GPU
driver is loaded.

Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

6 files changed, 154 insertions, 5 deletions

diff --git a/Documentation/mainboard/lenovo/t440p.md b/Documentation/mainboard/lenovo/t440p.md
index 98c1da54ac..fb0187075c 100644
--- a/Documentation/mainboard/lenovo/t440p.md
+++ b/Documentation/mainboard/lenovo/t440p.md
@@ -36,10 +36,7 @@ the laptop able to power on.
 - Cannot get the mainboard serial number from the mainboard: the OEM
   UEFI firmware gets the serial number from an "emulated EEPROM" via
   I/O port 0x1630/0x1634, but it's still unknown how to make it work
-
-## Untested
-
-- the dGPU model
+- The dGPU does not currently work in Windows.
 
 ## Working
 
@@ -61,6 +58,7 @@ the laptop able to power on.
 - CMOS options: wlan, trackpoint, fn_ctrl_swap
 - internal flashing when IFD is unlocked
 - using `me_cleaner`
+- dGPU (must be enabled in CMOS options)
 
 [Lenovo ThinkPad T440p]: https://pcsupport.lenovo.com/us/zh/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t440p
 [Hardware Maintenance Manual]: https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/t440p_hmm_en_sp40a25467_04.pdf
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index b9863367c9..73a20f2dfb 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -19,6 +19,7 @@ bootblock-y += bootblock.c
 
 ramstage-y += memmap.c
 ramstage-y += northbridge.c
+ramstage-y += pcie.c
 ramstage-y += gma.c
 
 ramstage-y += acpi.c
diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl
index 45ebff29f1..2db72d7842 100644
--- a/src/northbridge/intel/haswell/acpi/haswell.asl
+++ b/src/northbridge/intel/haswell/acpi/haswell.asl
@@ -16,6 +16,7 @@
 
 #include "../haswell.h"
 #include "hostbridge.asl"
+#include "peg.asl"
 #include <southbridge/intel/common/rcba.h>
 
 /* PCI Device Resource Consumption */
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index 19d788ce26..d567701cb7 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -36,7 +36,8 @@ Device (MCHC)
 		MHEN,	 1,	// Enable
 		,	13,	//
 		MHBR,	22,	// MCHBAR
-
+		Offset (0x54),
+		DVEN,	32,
 		Offset (0x60),	// PCIe BAR
 		PXEN,	 1,	// Enable
 		PXSZ,	 2,	// BAR size
diff --git a/src/northbridge/intel/haswell/acpi/peg.asl b/src/northbridge/intel/haswell/acpi/peg.asl
new file mode 100644
index 0000000000..c4af375422
--- /dev/null
+++ b/src/northbridge/intel/haswell/acpi/peg.asl
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017-2018 Patrick Rudolph <siro@das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Device (PEGP)
+{
+	Name (_ADR, 0x00010000)
+
+	Method (_STA)
+	{
+		Return (((\_SB.PCI0.MCHC.DVEN >> 3) & 1) * 0xf)
+	}
+
+	Device (DEV0)
+	{
+		Name(_ADR, 0x00000000)
+	}
+}
+
+Device (PEG1)
+{
+	Name (_ADR, 0x00010001)
+
+	Method (_STA)
+	{
+		Return (((\_SB.PCI0.MCHC.DVEN >> 2) & 1) * 0xf)
+	}
+
+	Device (DEV0)
+	{
+		Name(_ADR, 0x00000000)
+	}
+}
+
+Device (PEG2)
+{
+	Name (_ADR, 0x00010002)
+
+	Method (_STA)
+	{
+		Return (((\_SB.PCI0.MCHC.DVEN >> 1) & 1) * 0xf)
+	}
+
+	Device (DEV0)
+	{
+		Name(_ADR, 0x00000000)
+	}
+}
diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c
new file mode 100644
index 0000000000..b3a21bfc3e
--- /dev/null
+++ b/src/northbridge/intel/haswell/pcie.c
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017-2018 Patrick Rudolph <siro@das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <device/pci_ids.h>
+#include <assert.h>
+
+static void pcie_disable(struct device *dev)
+{
+	printk(BIOS_INFO, "%s: Disabling device\n", dev_path(dev));
+	dev->enabled = 0;
+}
+
+#if CONFIG(HAVE_ACPI_TABLES)
+static const char *pcie_acpi_name(const struct device *dev)
+{
+	assert(dev);
+
+	if (dev->path.type != DEVICE_PATH_PCI)
+		return NULL;
+
+	assert(dev->bus);
+	if (dev->bus->secondary == 0)
+		switch (dev->path.pci.devfn) {
+		case PCI_DEVFN(1, 0):
+			return "PEGP";
+		case PCI_DEVFN(1, 1):
+			return "PEG1";
+		case PCI_DEVFN(1, 2):
+			return "PEG2";
+		};
+
+	struct device *const port = dev->bus->dev;
+	assert(port);
+	assert(port->bus);
+
+	if (dev->path.pci.devfn == PCI_DEVFN(0, 0) &&
+	    port->bus->secondary == 0 &&
+	    (port->path.pci.devfn == PCI_DEVFN(1, 0) ||
+	    port->path.pci.devfn == PCI_DEVFN(1, 1) ||
+	    port->path.pci.devfn == PCI_DEVFN(1, 2)))
+		return "DEV0";
+
+	return NULL;
+}
+#endif
+
+static struct pci_operations pci_ops = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations device_ops = {
+	.read_resources		= pci_bus_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_bus_enable_resources,
+	.scan_bus		= pciexp_scan_bridge,
+	.reset_bus		= pci_bus_reset,
+	.disable		= pcie_disable,
+	.init			= pci_dev_init,
+	.ops_pci		= &pci_ops,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.acpi_name		= pcie_acpi_name,
+#endif
+};
+
+static const unsigned short pci_device_ids[] = { 0x0c01, 0x0c05, 0x0c09, 0x0c0d, 0 };
+
+static const struct pci_driver pch_pcie __pci_driver = {
+	.ops		= &device_ops,
+	.vendor		= PCI_VENDOR_ID_INTEL,
+	.devices	= pci_device_ids,
+};