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authorShelley Chen <shchen@google.com>2019-11-06 18:11:11 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-11-11 10:28:32 +0000
commit5c7b74a22bd69e5f41380eba1a3b3be61512d24d (patch)
tree9c3eaa81809d63596e8dff1e5c0662b0271cde29
parent56aeae0400df8843b62bea85d0dbe27aaf0be325 (diff)
Helios: Set the reset delay for Goodix touchscreen to 120ms
With the 0.71586+ Goodix FW, we can reduce the reset delay from 500ms to 120ms. We should do the change in coreboot device tree after we ensure Helios DVT build is flashed with 0.71586+ Goodix FW. BUG=b:142316026 BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I000ee4ea84c598b437992f1000f6e5b561cae605 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com>
-rw-r--r--src/mainboard/google/hatch/variants/hatch/overridetree.cb2
-rw-r--r--src/mainboard/google/hatch/variants/helios/overridetree.cb2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb
index bc6aa11cab..75c14efad5 100644
--- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb
@@ -98,7 +98,7 @@ chip soc/intel/cannonlake
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
- register "generic.reset_delay_ms" = "500"
+ register "generic.reset_delay_ms" = "120"
register "generic.reset_off_delay_ms" = "3"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
register "generic.enable_delay_ms" = "12"
diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb
index 04bf6c12af..94639dcabe 100644
--- a/src/mainboard/google/hatch/variants/helios/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb
@@ -103,7 +103,7 @@ chip soc/intel/cannonlake
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
- register "generic.reset_delay_ms" = "500"
+ register "generic.reset_delay_ms" = "120"
register "generic.reset_off_delay_ms" = "1"
register "generic.enable_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"