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authorRaihow Shi <raihow_shi@wistron.corp-partner.google.com>2022-02-24 11:09:43 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-03-22 19:01:46 +0000
commit5a0ad11868686795e8a8af6dd576a7c3a7f26fd6 (patch)
tree951a84819220556acc630975e9a56a8bad40dc45
parentf613ce04791e5253d1df94f9a236e4f2014f2fc6 (diff)
mb/google/brask/variants/moli: init overridetree for moli
init overridetree.cb based on the schematic adl_rfq_mb_20220310.pdf BUG=b:220814038 Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
-rw-r--r--src/mainboard/google/brya/variants/moli/overridetree.cb232
1 files changed, 229 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb
index 4f2c04a57a..a11f8e9d49 100644
--- a/src/mainboard/google/brya/variants/moli/overridetree.cb
+++ b/src/mainboard/google/brya/variants/moli/overridetree.cb
@@ -1,6 +1,232 @@
+fw_config
+ field DB_OPT 2 3
+ option OPT_ABSENT 0
+ option OPT_HDMI 1
+ option OPT_DP 2
+ end
+end
chip soc/intel/alderlake
-
- device domain 0 on
- end
+ # Enable HDMI2 in PortA, HDMI1 in PortB, HDMI/DP in Port2
+ register "ddi_ports_config" = "{
+ [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+ [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+ [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+ }"
+ register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_Type-A Port A2
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_Type-A Port A3
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2_Type-A Port A9
+ register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable TCP3
+ register "CnviBtAudioOffload" = "true"
+ device domain 0 on
+ device ref tcss_dma0 on
+ chip drivers/intel/usb4/retimer
+ register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+ use tcss_usb3_port1 as dfp[0].typec_port
+ device generic 0 on end
+ end
+ end
+ device ref pcie4_0 on
+ # Enable CPU PCIE RP 1 using CLK 0
+ register "cpu_pcie_rp[CPU_RP(1)]" = "{
+ .clk_req = 0,
+ .clk_src = 0,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ end # SSD gen4
+ device ref cnvi_wifi on
+ chip drivers/wifi/generic
+ register "wake" = "GPE0_PME_B0"
+ device generic 0 on end
+ end
+ end # WiFi
+ device ref i2c0 on
+ chip drivers/i2c/nau8825
+ register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
+ register "jkdet_enable" = "1"
+ register "jkdet_pull_enable" = "0"
+ register "jkdet_pull_up" = "0"
+ register "jkdet_polarity" = "1" # ActiveLow
+ register "vref_impedance" = "2" # 125kOhm
+ register "micbias_voltage" = "6" # 2.754
+ register "sar_threshold_num" = "4"
+ register "sar_threshold[0]" = "0x0C"
+ register "sar_threshold[1]" = "0x1C"
+ register "sar_threshold[2]" = "0x38"
+ register "sar_threshold[3]" = "0x60"
+ register "sar_hysteresis" = "1"
+ register "sar_voltage" = "6"
+ register "sar_compare_time" = "0" # 500ns
+ register "sar_sampling_time" = "0" # 2us
+ register "short_key_debounce" = "2" # 100ms
+ register "jack_insert_debounce" = "7" # 512ms
+ register "jack_eject_debounce" = "7" # 512ms
+ device i2c 1a on end
+ end
+ end # Audio Nau8825
+ device ref pcie_rp6 on
+ # Enable PCIe-to-i225 bridge PCIe 6 using clk 5
+ register "pch_pcie_rp[PCH_RP(6)]" = "{
+ .clk_src = 5,
+ .clk_req = 5,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ device pci 00.0 on end
+ end # IntelI225V Ethernet NIC
+ device ref pcie_rp7 on
+ chip drivers/net
+ register "customized_leds" = "0x05af"
+ register "wake" = "GPE0_DW0_07"
+ register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H22)"
+ register "stop_delay_ms" = "12" # NIC needs time to quiesce
+ register "stop_off_delay_ms" = "1"
+ register "has_power_resource" = "1"
+ register "device_index" = "0"
+ device pci 00.0 on end
+ end
+ end # RTL8111K Ethernet NIC
+ device ref pcie_rp8 on
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
+ register "srcclk_pin" = "3"
+ device generic 0 on end
+ end
+ end # PCIE8 SD card
+ device ref pcie_rp9 off end #pcie_rp 9 Empty
+ device ref pcie_rp10 off end #pcie_rp 10 Empty
+ device ref pcie_rp11 off end #pcie_rp 11 Empty
+ device ref pcie_rp12 on
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
+ register "srcclk_pin" = "1"
+ device generic 0 alias emmc_rtd3 on end
+ end # Enable PCIe-to-eMMC bridge PCIE 12 using clk 1
+ register "pch_pcie_rp[PCH_RP(12)]" = "{
+ .clk_src = 1,
+ .clk_req = 1,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ end # PCIE12 BH799BB
+ device ref pch_espi on
+ chip ec/google/chromeec
+ use conn0 as mux_conn[0]
+ device pnp 0c09.0 on end
+ end
+ end
+ device ref pmc hidden
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ use usb2_port1 as usb2_port
+ use tcss_usb3_port1 as usb3_port
+ device generic 0 alias conn0 on end
+ end
+ end
+ end
+ end
+ device ref tcss_xhci on
+ chip drivers/usb/acpi
+ device ref tcss_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C0 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
+ device ref tcss_usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C2 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+ device ref tcss_usb3_port2 on end
+ end
+ end
+ end
+ end
+ device ref xhci on
+ chip drivers/usb/acpi
+ device ref xhci_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C0 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
+ device ref usb2_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C2 (MLB)""
+ register "type" = "UPC_TYPE_A"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+ device ref usb2_port3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A4 (MLB)""
+ register "type" = "UPC_TYPE_A"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
+ device ref usb2_port4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 NFC""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device ref usb2_port5 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A3 (MLB)""
+ register "type" = "UPC_TYPE_A"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
+ device ref usb2_port6 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A2 (MLB)""
+ register "type" = "UPC_TYPE_A"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(6, 1))"
+ device ref usb2_port7 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A1 (MLB)""
+ register "type" = "UPC_TYPE_A"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(7, 1))"
+ device ref usb2_port8 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+ device ref usb2_port10 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A1 (MLB)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(7, 2))"
+ device ref usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A2 (MLB)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(6, 1))"
+ device ref usb3_port2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A3 (MLB)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
+ device ref usb3_port3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A4 (MLB)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
+ device ref usb3_port4 on end
+ end
+ end
+ end
+ end #USB2 and USB3 Port
+ device ref i2c1 on
+ chip drivers/i2c/tpm
+ register "hid" = ""GOOG0005""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+ device i2c 50 on end
+ end
+ end # tpm
+ end
end