diff options
| author | Damien Zammit <damien@zamaudio.com> | 2016-01-22 22:12:30 +1100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-29 00:27:09 +0100 |
| commit | 5680fafb4d2cdc1d914226ff4d01b9b12ba75097 (patch) | |
| tree | 43e344b201063dfbf03f6c09366ab9383939afed | |
| parent | 216fc50411a354917cee97b243cdb1dbf1e0a76d (diff) | |
nb/intel/x4x: Move to early cbmem
Previously with errors in the ram init, early cbmem was disabled.
Now that the ram is working correctly, set as early cbmem platform
and update all (1) boards to use it.
Tested on GA-G41M-ES2L
Change-Id: I5925c28821537f0e326b4f5a2ac39778e4724a3c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13131
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
| -rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/Kconfig | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/northbridge.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/ram_calc.c | 7 |
4 files changed, 9 insertions, 4 deletions
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 6bae12814c..ca8ca5c071 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -159,5 +159,6 @@ void main(unsigned long bist) printk(BIOS_DEBUG, "Initializing memory\n"); sdram_initialize(0, spd_addrmap); quick_ram_check(); + cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); } diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index c330fd50d5..f643bb2a8d 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -26,7 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT_DEFAULT select VGA select INTEL_GMA_ACPI - select LATE_CBMEM_INIT + select EARLY_CBMEM_INIT config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 0fe8901957..2d6c39f365 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -29,7 +29,6 @@ #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/chip.h> #include <northbridge/intel/x4x/x4x.h> -#include <cbmem.h> static void mch_domain_read_resources(device_t dev) { @@ -112,8 +111,6 @@ static void mch_domain_read_resources(device_t dev) fixed_mem_resource(dev, index++, pcie_config_base >> 10, pcie_config_size >> 10, IORESOURCE_RESERVE); } - - set_top_of_ram(usable_tomk * 1024); } static void mch_domain_set_resources(device_t dev) diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index f11b19a9f1..27562eae83 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -17,6 +17,7 @@ #define __SIMPLE_DEVICE__ +#include <cbmem.h> #include <commonlib/helpers.h> #include <stdint.h> #include <arch/io.h> @@ -86,3 +87,9 @@ u8 decode_pciebar(u32 *const base, u32 *const len) *len = max_buses << 20; return 1; } + +void *cbmem_top(void) +{ + u32 ramtop = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG); + return (void*)(ramtop); +} |