soc/amd/*/i2c: factor out common I2C pad configuration

The I2C pad control registers of Picasso and Cezanne are identical and
the one of Sabrina is a superset of it, so factor out the functionality.
To avoid having devicetree settings that contain raw register bits, the
i2c_pad_control struct is introduced and used. The old Picasso code for
this had the RX level hard-coded for 3.3V I2C interfaces, so keep it
this way in this patch but add a TODO  for future improvements.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

19 files changed, 134 insertions, 145 deletions

diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb
index 19815b3681..6067b18ebf 100644
--- a/src/mainboard/amd/chausie/devicetree.cb
+++ b/src/mainboard/amd/chausie/devicetree.cb
@@ -14,10 +14,10 @@ chip soc/amd/sabrina
 	}"
 
 	# I2C Pad Control RX Select Configuration
-	register "i2c_pad_ctrl_rx_sel[0]" = "I2C_PAD_CTRL_RX_SEL_3_3V"
-	register "i2c_pad_ctrl_rx_sel[1]" = "I2C_PAD_CTRL_RX_SEL_3_3V"
-	register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V"
-	register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_3_3V"
+	register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V"
+	register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V"
+	register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V"
+	register "i2c_pad[3].rx_level" = "I2C_PAD_RX_3_3V"
 
 	register "s0ix_enable" = "true"
 
diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb
index 7bb0db1e33..9758e9cf2d 100644
--- a/src/mainboard/amd/majolica/devicetree.cb
+++ b/src/mainboard/amd/majolica/devicetree.cb
@@ -14,10 +14,10 @@ chip soc/amd/cezanne
 	}"
 
 	# I2C Pad Control RX Select Configuration
-	register "i2c_pad_ctrl_rx_sel[0]" = "I2C_PAD_CTRL_RX_SEL_3_3V"
-	register "i2c_pad_ctrl_rx_sel[1]" = "I2C_PAD_CTRL_RX_SEL_3_3V"
-	register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V"
-	register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_3_3V"
+	register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V"
+	register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V"
+	register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V"
+	register "i2c_pad[3].rx_level" = "I2C_PAD_RX_3_3V"
 
 	register "s0ix_enable" = "true"
 
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
index ac2856e93b..104ba79c43 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
@@ -75,10 +75,10 @@ chip soc/amd/cezanne
 	register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
 					GPIO_I2C2_SCL | GPIO_I2C3_SCL"
 	# I2C Pad Control RX Select Configuration
-	register "i2c_pad_ctrl_rx_sel[0]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Trackpad
-	register "i2c_pad_ctrl_rx_sel[1]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Touchscreen
-	register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Audio/SAR
-	register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_1_8V" # GSC
+	register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V" # Trackpad
+	register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V" # Touchscreen
+	register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V" # Audio/SAR
+	register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC
 
 	# general purpose PCIe clock output configuration
 	register "gpp_clk_config[0]" = "GPP_CLK_REQ"
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 620c650ba1..f0b7c272d4 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -50,6 +50,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_GRAPHICS
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI
 	select SOC_AMD_COMMON_BLOCK_I2C
+	select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL
 	select SOC_AMD_COMMON_BLOCK_IOMMU
 	select SOC_AMD_COMMON_BLOCK_LPC
 	select SOC_AMD_COMMON_BLOCK_MCAX
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h
index d007a84c98..1e59153ef5 100644
--- a/src/soc/amd/cezanne/chip.h
+++ b/src/soc/amd/cezanne/chip.h
@@ -4,6 +4,7 @@
 #define CEZANNE_CHIP_H
 
 #include <amdblocks/chip.h>
+#include <amdblocks/i2c.h>
 #include <gpio.h>
 #include <soc/i2c.h>
 #include <soc/southbridge.h>
@@ -15,7 +16,7 @@ struct soc_amd_cezanne_config {
 	struct soc_amd_common_config common_config;
 	u8 i2c_scl_reset;
 	struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
-	u8 i2c_pad_ctrl_rx_sel[I2C_CTRLR_COUNT];
+	struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT];
 
 	/* Enable S0iX support */
 	bool s0ix_enable;
diff --git a/src/soc/amd/cezanne/i2c.c b/src/soc/amd/cezanne/i2c.c
index 1fcab6a0db..bf47b81462 100644
--- a/src/soc/amd/cezanne/i2c.c
+++ b/src/soc/amd/cezanne/i2c.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <amdblocks/acpimmio.h>
 #include <amdblocks/i2c.h>
 #include <console/console.h>
 #include <soc/i2c.h>
@@ -36,24 +35,11 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar)
 void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
 {
 	const struct soc_amd_cezanne_config *config = config_of_soc();
-	uint32_t pad_ctrl;
 
-	if (bus >= ARRAY_SIZE(config->i2c_pad_ctrl_rx_sel))
+	if (bus >= ARRAY_SIZE(config->i2c_pad))
 		return;
 
-	pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus));
-
-	pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK;
-	pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL;
-
-	pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK;
-	pad_ctrl |= config->i2c_pad_ctrl_rx_sel[bus];
-
-	pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK;
-	pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ?
-		I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW;
-	pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN;
-	misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl);
+	fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]);
 }
 
 const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index 9c68d38352..4e44b89fe4 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -112,33 +112,6 @@
 #define MISC_CLK_CNTL0			0x40 /* named MISC_CLK_CNTL1 on Picasso */
 #define   BP_X48M0_S0I3_DIS		BIT(4)
 #define   BP_X48M0_OUTPUT_EN		BIT(2) /* 1=En, unlike Hudson, Kern */
-#define MISC_I2C0_PAD_CTRL		0xd8
-#define MISC_I2C1_PAD_CTRL		0xdc
-#define MISC_I2C2_PAD_CTRL		0xe0
-#define MISC_I2C3_PAD_CTRL		0xe4
-#define MISC_I2C_PAD_CTRL(bus)		(MISC_I2C0_PAD_CTRL + 4 * (bus))
-#define   I2C_PAD_CTRL_NG_MASK		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
-#define     I2C_PAD_CTRL_NG_NORMAL	0xc
-#define   I2C_PAD_CTRL_RX_SEL_MASK	(BIT(4) | BIT(5))
-#define     I2C_PAD_CTRL_RX_SHIFT	4
-#define     I2C_PAD_CTRL_RX_SEL_OFF	(0 << I2C_PAD_CTRL_RX_SHIFT)
-#define     I2C_PAD_CTRL_RX_SEL_3_3V	(1 << I2C_PAD_CTRL_RX_SHIFT)
-#define     I2C_PAD_CTRL_RX_SEL_1_8V	(3 << I2C_PAD_CTRL_RX_SHIFT)
-#define   I2C_PAD_CTRL_PULLDOWN_EN	BIT(6)
-#define   I2C_PAD_CTRL_FALLSLEW_MASK	(BIT(7) | BIT(8))
-#define     I2C_PAD_CTRL_FALLSLEW_SHIFT	7
-#define     I2C_PAD_CTRL_FALLSLEW_STD	(0 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
-#define     I2C_PAD_CTRL_FALLSLEW_LOW	(1 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
-#define   I2C_PAD_CTRL_FALLSLEW_EN	BIT(9)
-#define   I2C_PAD_CTRL_SPIKE_RC_EN	BIT(10)
-#define   I2C_PAD_CTRL_SPIKE_RC_SEL	BIT(11) /* 0 = 50ns, 1 = 20ns */
-#define   I2C_PAD_CTRL_CAP_DOWN		BIT(12)
-#define   I2C_PAD_CTRL_CAP_UP		BIT(13)
-#define   I2C_PAD_CTRL_RES_DOWN		BIT(14)
-#define   I2C_PAD_CTRL_RES_UP		BIT(15)
-#define   I2C_PAD_CTRL_BIAS_CRT_EN	BIT(16)
-#define   I2C_PAD_CTRL_SPARE0		BIT(17)
-#define   I2C_PAD_CTRL_SPARE1		BIT(18)
 
 void fch_pre_init(void);
 void fch_early_init(void);
diff --git a/src/soc/amd/common/block/i2c/Kconfig b/src/soc/amd/common/block/i2c/Kconfig
index 5d8498c6af..7c1ea0edd8 100644
--- a/src/soc/amd/common/block/i2c/Kconfig
+++ b/src/soc/amd/common/block/i2c/Kconfig
@@ -2,3 +2,9 @@ config SOC_AMD_COMMON_BLOCK_I2C
 	bool
 	help
 	  Select this option to add FCH I2C controller functions to the build.
+
+config SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL
+	bool
+	help
+	  Select this option to add FCH I2C pad configuration functions to the
+	  build.
diff --git a/src/soc/amd/common/block/i2c/Makefile.inc b/src/soc/amd/common/block/i2c/Makefile.inc
index 8af77965ce..3d2cdf6e09 100644
--- a/src/soc/amd/common/block/i2c/Makefile.inc
+++ b/src/soc/amd/common/block/i2c/Makefile.inc
@@ -1 +1,2 @@
 all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C) += i2c.c
+all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL) += i2c_pad_ctrl.c
diff --git a/src/soc/amd/common/block/i2c/i2c_pad_ctrl.c b/src/soc/amd/common/block/i2c/i2c_pad_ctrl.c
new file mode 100644
index 0000000000..cdb7900ee6
--- /dev/null
+++ b/src/soc/amd/common/block/i2c/i2c_pad_ctrl.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/i2c.h>
+#include <console/console.h>
+#include <types.h>
+#include "i2c_pad_def.h"
+
+void fch_i2c_pad_init(unsigned int bus,
+		      enum i2c_speed speed,
+		      const struct i2c_pad_control *ctrl)
+{
+	uint32_t pad_ctrl;
+
+	pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus));
+
+	pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK;
+	pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL;
+
+	switch (ctrl->rx_level) {
+	case I2C_PAD_RX_NO_CHANGE:
+		break;
+	case I2C_PAD_RX_OFF:
+		pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK;
+		pad_ctrl |= I2C_PAD_CTRL_RX_SEL_OFF;
+		break;
+	case I2C_PAD_RX_3_3V:
+		pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK;
+		pad_ctrl |= I2C_PAD_CTRL_RX_SEL_3_3V;
+		break;
+	case I2C_PAD_RX_1_8V:
+		pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK;
+		pad_ctrl |= I2C_PAD_CTRL_RX_SEL_1_8V;
+		break;
+	default:
+		printk(BIOS_WARNING, "Invalid I2C pad RX level for bus %u\n", bus);
+		break;
+	}
+
+	pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK;
+	pad_ctrl |= speed == I2C_SPEED_STANDARD ?
+		I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW;
+	pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN;
+	misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl);
+}
diff --git a/src/soc/amd/common/block/i2c/i2c_pad_def.h b/src/soc/amd/common/block/i2c/i2c_pad_def.h
new file mode 100644
index 0000000000..76e10cd545
--- /dev/null
+++ b/src/soc/amd/common/block/i2c/i2c_pad_def.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_BLOCK_I2C_PAD_DEF_H
+#define AMD_BLOCK_I2C_PAD_DEF_H
+
+#include <types.h>
+
+#define MISC_I2C0_PAD_CTRL		0xd8
+#define MISC_I2C_PAD_CTRL(bus)		(MISC_I2C0_PAD_CTRL + 4 * (bus))
+
+#define   I2C_PAD_CTRL_NG_MASK		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
+#define     I2C_PAD_CTRL_NG_NORMAL	0xc
+#define   I2C_PAD_CTRL_RX_SEL_MASK	(BIT(4) | BIT(5))
+#define     I2C_PAD_CTRL_RX_SHIFT	4
+#define     I2C_PAD_CTRL_RX_SEL_OFF	(0 << I2C_PAD_CTRL_RX_SHIFT)
+#define     I2C_PAD_CTRL_RX_SEL_3_3V	(1 << I2C_PAD_CTRL_RX_SHIFT)
+#define     I2C_PAD_CTRL_RX_SEL_1_8V	(3 << I2C_PAD_CTRL_RX_SHIFT)
+#define   I2C_PAD_CTRL_PULLDOWN_EN	BIT(6)
+#define   I2C_PAD_CTRL_FALLSLEW_MASK	(BIT(7) | BIT(8))
+#define     I2C_PAD_CTRL_FALLSLEW_SHIFT	7
+#define     I2C_PAD_CTRL_FALLSLEW_STD	(0 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
+#define     I2C_PAD_CTRL_FALLSLEW_LOW	(1 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
+#define   I2C_PAD_CTRL_FALLSLEW_EN	BIT(9)
+#define   I2C_PAD_CTRL_SPIKE_RC_EN	BIT(10)
+#define   I2C_PAD_CTRL_SPIKE_RC_SEL	BIT(11) /* 0 = 50ns, 1 = 20ns */
+#define   I2C_PAD_CTRL_CAP_DOWN		BIT(12)
+#define   I2C_PAD_CTRL_CAP_UP		BIT(13)
+#define   I2C_PAD_CTRL_RES_DOWN		BIT(14)
+#define   I2C_PAD_CTRL_RES_UP		BIT(15)
+#define   I2C_PAD_CTRL_BIAS_CRT_EN	BIT(16)
+#define   I2C_PAD_CTRL_SPARE0		BIT(17)
+#define   I2C_PAD_CTRL_SPARE1		BIT(18)
+/* The following bits are reserved in Picasso and Cezanne */
+#define   I2C_PAD_CTRL_PD_EN		BIT(19)
+#define   I2C_PAD_CTRL_COMP_SEL		BIT(20)
+#define   I2C_PAD_CTRL_RES_BIAS_EN	BIT(21)
+
+#endif /* AMD_BLOCK_I2C_PAD_DEF_H */
diff --git a/src/soc/amd/common/block/include/amdblocks/i2c.h b/src/soc/amd/common/block/include/amdblocks/i2c.h
index 6660e3779c..54651a9321 100644
--- a/src/soc/amd/common/block/include/amdblocks/i2c.h
+++ b/src/soc/amd/common/block/include/amdblocks/i2c.h
@@ -56,6 +56,21 @@ struct soc_i2c_peripheral_reset_info {
 	size_t num_pins;
 };
 
+enum i2c_pad_rx_level {
+	I2C_PAD_RX_NO_CHANGE,
+	I2C_PAD_RX_OFF,
+	I2C_PAD_RX_3_3V,
+	I2C_PAD_RX_1_8V,
+};
+
+struct i2c_pad_control {
+	enum i2c_pad_rx_level rx_level;
+};
+
+void fch_i2c_pad_init(unsigned int bus,
+		      enum i2c_speed speed,
+		      const struct i2c_pad_control *ctrl);
+
 /* Helper function to perform misc I2C configuration specific to SoC. */
 void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg);
 
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 4567d5558b..ebcbd62068 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI
 	select SOC_AMD_COMMON_BLOCK_HDA
 	select SOC_AMD_COMMON_BLOCK_I2C
+	select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL
 	select SOC_AMD_COMMON_BLOCK_IOMMU
 	select SOC_AMD_COMMON_BLOCK_LPC
 	select SOC_AMD_COMMON_BLOCK_MCAX
diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c
index 40cf556b04..ebc833df2a 100644
--- a/src/soc/amd/picasso/i2c.c
+++ b/src/soc/amd/picasso/i2c.c
@@ -40,22 +40,13 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar)
 
 void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
 {
-	uint32_t pad_ctrl;
+	/* TODO: Picasso supports I2C RX pad configurations 3.3V, 1.8V and off, so make this
+	   configurable. */
+	const struct i2c_pad_control ctrl = {
+		.rx_level = I2C_PAD_RX_3_3V,
+	};
 
-	pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus));
-
-	pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK;
-	pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL;
-
-	pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK;
-	pad_ctrl |= I2C_PAD_CTRL_RX_SEL_3_3V;
-
-	pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK;
-	pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ?
-		I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW;
-	pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN;
-
-	misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl);
+	fch_i2c_pad_init(bus, cfg->speed, &ctrl);
 }
 
 const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 2a3e38b43c..b8dd67b5c7 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -92,33 +92,6 @@
 #define   CG1PLL_SPREAD_SPECTRUM_ENABLE	BIT(0)
 #define MISC_CLK_CNTL1			0x40
 #define   BP_X48M0_OUTPUT_EN		BIT(2) /* 1=En, unlike Hudson, Kern */
-#define MISC_I2C0_PAD_CTRL		0xd8
-#define MISC_I2C1_PAD_CTRL		0xdc
-#define MISC_I2C2_PAD_CTRL		0xe0
-#define MISC_I2C3_PAD_CTRL		0xe4
-#define MISC_I2C_PAD_CTRL(bus)		(MISC_I2C0_PAD_CTRL + 4 * (bus))
-#define   I2C_PAD_CTRL_NG_MASK		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
-#define     I2C_PAD_CTRL_NG_NORMAL	0xc
-#define   I2C_PAD_CTRL_RX_SEL_MASK	(BIT(4) | BIT(5))
-#define     I2C_PAD_CTRL_RX_SHIFT	4
-#define     I2C_PAD_CTRL_RX_SEL_OFF	(0 << I2C_PAD_CTRL_RX_SHIFT)
-#define     I2C_PAD_CTRL_RX_SEL_3_3V	(1 << I2C_PAD_CTRL_RX_SHIFT)
-#define     I2C_PAD_CTRL_RX_SEL_1_8V	(3 << I2C_PAD_CTRL_RX_SHIFT)
-#define   I2C_PAD_CTRL_PULLDOWN_EN	BIT(6)
-#define   I2C_PAD_CTRL_FALLSLEW_MASK	(BIT(7) | BIT(8))
-#define     I2C_PAD_CTRL_FALLSLEW_SHIFT	7
-#define     I2C_PAD_CTRL_FALLSLEW_STD	(0 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
-#define     I2C_PAD_CTRL_FALLSLEW_LOW	(1 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
-#define   I2C_PAD_CTRL_FALLSLEW_EN	BIT(9)
-#define   I2C_PAD_CTRL_SPIKE_RC_EN	BIT(10)
-#define   I2C_PAD_CTRL_SPIKE_RC_SEL	BIT(11) /* 0 = 50ns, 1 = 20ns */
-#define   I2C_PAD_CTRL_CAP_DOWN		BIT(12)
-#define   I2C_PAD_CTRL_CAP_UP		BIT(13)
-#define   I2C_PAD_CTRL_RES_DOWN		BIT(14)
-#define   I2C_PAD_CTRL_RES_UP		BIT(15)
-#define   I2C_PAD_CTRL_BIAS_CRT_EN	BIT(16)
-#define   I2C_PAD_CTRL_SPARE0		BIT(17)
-#define   I2C_PAD_CTRL_SPARE1		BIT(18)
 
 #define FCH_LEGACY_UART_DECODE		(ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
 
diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig
index ca7a83c5e7..2e34e3f519 100644
--- a/src/soc/amd/sabrina/Kconfig
+++ b/src/soc/amd/sabrina/Kconfig
@@ -52,6 +52,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_GRAPHICS	# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI	# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_I2C		# TODO: Check if this is still correct
+	select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL
 	select SOC_AMD_COMMON_BLOCK_IOMMU	# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_LPC		# TODO: Check if this is still correct
 	select SOC_AMD_COMMON_BLOCK_MCAX	# TODO: Check if this is still correct
diff --git a/src/soc/amd/sabrina/chip.h b/src/soc/amd/sabrina/chip.h
index a7acb7f29f..c272f9f2dc 100644
--- a/src/soc/amd/sabrina/chip.h
+++ b/src/soc/amd/sabrina/chip.h
@@ -6,6 +6,7 @@
 #define SABRINA_CHIP_H
 
 #include <amdblocks/chip.h>
+#include <amdblocks/i2c.h>
 #include <gpio.h>
 #include <soc/i2c.h>
 #include <soc/southbridge.h>
@@ -17,7 +18,7 @@ struct soc_amd_sabrina_config {
 	struct soc_amd_common_config common_config;
 	u8 i2c_scl_reset;
 	struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
-	u8 i2c_pad_ctrl_rx_sel[I2C_CTRLR_COUNT];
+	struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT];
 
 	/* Enable S0iX support */
 	bool s0ix_enable;
diff --git a/src/soc/amd/sabrina/i2c.c b/src/soc/amd/sabrina/i2c.c
index 89751d5d43..88da74e224 100644
--- a/src/soc/amd/sabrina/i2c.c
+++ b/src/soc/amd/sabrina/i2c.c
@@ -2,7 +2,6 @@
 
 /* TODO: Check if this is still correct */
 
-#include <amdblocks/acpimmio.h>
 #include <amdblocks/i2c.h>
 #include <console/console.h>
 #include <soc/i2c.h>
@@ -38,24 +37,11 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar)
 void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
 {
 	const struct soc_amd_sabrina_config *config = config_of_soc();
-	uint32_t pad_ctrl;
 
-	if (bus >= ARRAY_SIZE(config->i2c_pad_ctrl_rx_sel))
+	if (bus >= ARRAY_SIZE(config->i2c_pad))
 		return;
 
-	pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus));
-
-	pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK;
-	pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL;
-
-	pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK;
-	pad_ctrl |= config->i2c_pad_ctrl_rx_sel[bus];
-
-	pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK;
-	pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ?
-		I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW;
-	pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN;
-	misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl);
+	fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]);
 }
 
 const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
diff --git a/src/soc/amd/sabrina/include/soc/southbridge.h b/src/soc/amd/sabrina/include/soc/southbridge.h
index e85a052a3a..e755d5019c 100644
--- a/src/soc/amd/sabrina/include/soc/southbridge.h
+++ b/src/soc/amd/sabrina/include/soc/southbridge.h
@@ -113,36 +113,6 @@
 #define MISC_CLK_CNTL0			0x40 /* named MISC_CLK_CNTL1 on Picasso */
 #define   BP_X48M0_S0I3_DIS		BIT(4)
 #define   BP_X48M0_OUTPUT_EN		BIT(2) /* 1=En, unlike Hudson, Kern */
-#define MISC_I2C0_PAD_CTRL		0xd8
-#define MISC_I2C1_PAD_CTRL		0xdc
-#define MISC_I2C2_PAD_CTRL		0xe0
-#define MISC_I2C3_PAD_CTRL		0xe4
-#define MISC_I2C_PAD_CTRL(bus)		(MISC_I2C0_PAD_CTRL + 4 * (bus))
-#define   I2C_PAD_CTRL_NG_MASK		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
-#define     I2C_PAD_CTRL_NG_NORMAL	0xc
-#define   I2C_PAD_CTRL_RX_SEL_MASK	(BIT(4) | BIT(5))
-#define     I2C_PAD_CTRL_RX_SHIFT	4
-#define     I2C_PAD_CTRL_RX_SEL_OFF	(0 << I2C_PAD_CTRL_RX_SHIFT)
-#define     I2C_PAD_CTRL_RX_SEL_3_3V	(1 << I2C_PAD_CTRL_RX_SHIFT)
-#define     I2C_PAD_CTRL_RX_SEL_1_8V	(3 << I2C_PAD_CTRL_RX_SHIFT)
-#define   I2C_PAD_CTRL_PULLDOWN_EN	BIT(6)
-#define   I2C_PAD_CTRL_FALLSLEW_MASK	(BIT(7) | BIT(8))
-#define     I2C_PAD_CTRL_FALLSLEW_SHIFT	7
-#define     I2C_PAD_CTRL_FALLSLEW_STD	(0 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
-#define     I2C_PAD_CTRL_FALLSLEW_LOW	(1 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
-#define   I2C_PAD_CTRL_FALLSLEW_EN	BIT(9)
-#define   I2C_PAD_CTRL_SPIKE_RC_EN	BIT(10)
-#define   I2C_PAD_CTRL_SPIKE_RC_SEL	BIT(11) /* 0 = 50ns, 1 = 20ns */
-#define   I2C_PAD_CTRL_CAP_DOWN		BIT(12)
-#define   I2C_PAD_CTRL_CAP_UP		BIT(13)
-#define   I2C_PAD_CTRL_RES_DOWN		BIT(14)
-#define   I2C_PAD_CTRL_RES_UP		BIT(15)
-#define   I2C_PAD_CTRL_BIAS_CRT_EN	BIT(16)
-#define   I2C_PAD_CTRL_SPARE0		BIT(17)
-#define   I2C_PAD_CTRL_SPARE1		BIT(18)
-#define   I2C_PAD_CTRL_PD_EN		BIT(19)
-#define   I2C_PAD_CTRL_COMP_SEL		BIT(20)
-#define   I2C_PAD_CTRL_RES_BIAS_EN	BIT(21)
 
 void fch_pre_init(void);
 void fch_early_init(void);