diff options
| author | Jenny TC <jenny.tc@intel.com> | 2015-06-18 14:02:00 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-29 19:26:34 +0200 |
| commit | 5468e94df1f1f017a936a2a619e57741ecfbd132 (patch) | |
| tree | 1285bad94a043a49503e55242c485ef896f825dc | |
| parent | 153ae105e5c928982b50d1599e626ae6ff494824 (diff) | |
intel/braswell: fix build
Commit "BCRD2: Enable LPDDR3" with the Change-Id listed below contained
additions to braswell's chip.h which were lost during merging.
BRANCH=None
BUG=None
TEST=google/strago builds
Change-Id: I995b788b6a308cefa23228544127bb1e384bbcc7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 561edf23ab696772fd0a6af34cb435db9d96e912
Original-Change-Id: Ie08900bc62d517394412cc597274fb8f5b6b0f51
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Original-Change-Id: I1cb5a03b77baf2df125b648dd75c9f8166f5571e
Original-Original-Signed-off-by: Jenny TC <jenny.tc@intel.com>
Original-Original-Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Original-Reviewed-on: https://chromium-review.googlesource.com/282155
Original-Reviewed-on: https://chromium-review.googlesource.com/288880
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/11065
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/soc/intel/braswell/chip.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 7422bc4c09..191fc01926 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -34,6 +34,9 @@ #define SVID_CONFIG3 3 #define SVID_PMIC_CONFIG 8 +#define MEM_DDR3 0 +#define MEM_LPDDR3 1 + struct soc_intel_braswell_config { uint8_t enable_xdp_tap; uint8_t clkreq_enable; |