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authorNaresh Solanki <Naresh.Solanki@9elements.com>2023-08-10 13:21:44 +0200
committerLean Sheng Tan <sheng.tan@9elements.com>2023-12-13 14:27:09 +0000
commit54662610197d7304b48d8e85a5b13263db3357f2 (patch)
tree757cc0560b30e2099ee6c3892bfdf731eca5e3e1
parent3e25f85d68d10249473d422c4c19dc30ea55e8b0 (diff)
drivers/uart/pl011.c Perform basic UART init
Configure UART baud rate, Line Control register as 8n1 with FIFO enable and enable UART TX and RX. Change-Id: I090344a20430dc370a0b93ff7fbbae54111fae24 Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79406 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
-rw-r--r--src/drivers/uart/pl011.c32
1 files changed, 32 insertions, 0 deletions
diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c
index 64c279d1b4..06782a3b98 100644
--- a/src/drivers/uart/pl011.c
+++ b/src/drivers/uart/pl011.c
@@ -7,6 +7,38 @@
void uart_init(unsigned int idx)
{
+ struct pl011_uart *regs = uart_platform_baseptr(idx);
+ uint32_t tmp;
+
+ if (!regs)
+ return;
+
+ /* Disable UART */
+ tmp = read32(&regs->cr);
+ tmp &= ~PL011_UARTCR_UARTEN;
+ write32(&regs->cr, tmp);
+
+ /*
+ * Program Divisor
+ * As per: PL011 Technical reference manual:
+ * BAUDDIV = (Fuartclk / (16 * baud_rate))
+ * Considering 6 bits(64) for UARTFBRD
+ * BAUDDIV = (Fuartclk * 4 / baud_rate)
+ */
+ tmp = uart_platform_refclk() * 4 / get_uart_baudrate();
+
+ write32(&regs->ibrd, tmp >> 6);
+ write32(&regs->fbrd, tmp & 0x3f);
+
+ /* Program LINE Control 8n1, FIFO enable */
+ tmp = read32(&regs->lcr_h);
+ tmp |= PL011_LINE_CONTROL;
+ write32(&regs->lcr_h, tmp);
+
+ /* Enable UART */
+ tmp = read32(&regs->cr);
+ tmp |= PL011_UARTCR_UARTEN | PL011_UARTCR_RXE | PL011_UARTCR_TXE;
+ write32(&regs->cr, tmp);
}
void uart_tx_byte(unsigned int idx, unsigned char data)