diff options
| author | Kevin Chiu <kevin.chiu.17802@gmail.com> | 2022-10-06 19:18:04 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-02 21:35:01 +0000 |
| commit | 53cfdc8660ef7771fcb3ea9af2586e26157a619f (patch) | |
| tree | c8d7d3a73732b2a371e29bf5dc8076be541156dd | |
| parent | 83e9456676b1066b8332756214058cd7f5584451 (diff) | |
mb/google/brya: enable PCIe RP12 for lisbon eMMC support
BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Ief8ca9cf845156ac761556d0eb49edb65894c001
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/lisbon/overridetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb index a2a40431ac..67b0d9b41f 100644 --- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb +++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb @@ -200,6 +200,14 @@ chip soc/intel/alderlake device generic 0 on end end end #PCIE8 SD card + device ref pcie_rp12 on + # Enable PCIE eMMC bridge 12 using clk 4 + register "pch_pcie_rp[PCH_RP(12)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, + }" + end #PCIE12 EMMC device ref gspi1 off end device ref pch_espi on chip ec/google/chromeec |