diff options
| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2023-10-17 19:26:31 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-10-20 17:51:52 +0000 |
| commit | 533efb23083afd721d4c268ce0ee8e863e13689a (patch) | |
| tree | 3b496ee4d9d3bf3fb35eead94ed1d7aec4ebeba2 | |
| parent | 6dff1fd7d5e419b2f947f516551dcab3f4ebe30a (diff) | |
soc/intel/meteorlake: Set build time physical address reserved bits
Meteor Lake TME bits [42-45] are reserved regardless of if the part
supports TME or not.
On a device with TME fused off, we noticed some reboot hangs which
have been narrowed down to internal IP routing issues when the IA
accesses the Input Output Manager (IOM) which is mapped at
0x3fff0aa0000 (0x3ff upper 32 bits).
It turns out since TME is fused off, coreboot uses the full physical
address size reported by CPUID MAXPHYADDR (46 bits). Therefore, it
allocates thunderbolt memory range on 46 bits (0x3fff upper 32 bits).
Since 4 of these bits are actually reserved, it seems that this
address range is "stripped down" to 42 bits (=> 0x3ff upper 32 bits)
resulting in potential conflict with other devices such as IOM.
BUG=b:288978352
TEST=No reboot issue on rex with TME fused off
Change-Id: I96ba23ab304257003c0413243d3ac8129ce31743
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78452
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/meteorlake/Kconfig | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 5ae6850884..d0db3e2b2e 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -452,4 +452,7 @@ config SOC_INTEL_COMMON_BLOCK_ACPI_SLP_S0_FREQ_HZ help slp_s0_residency granularity in 122us ticks (i.e. ~8.2KHz) in Meteor Lake. +config CPU_INTEL_COMMON_RESERVED_PHYS_ADDR_BITS + default 4 + endif |