diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-11-24 20:43:37 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-12-02 07:51:42 +0000 |
| commit | 5214c4091f2c747616873f37c086dbd57387f6a0 (patch) | |
| tree | 0d0a36b189b7ec2241822488beea6299964c2b72 | |
| parent | bed82b0c40b62736323a26a36a114b39c3c77a45 (diff) | |
soc/intel/cmn/cse: Send EOP cmd from .final aka `cse_final()`
This patch refactors common code to allow cse_final() function to send
EOP cmd if the SoC user selects `SOC_INTEL_CSE_SET_EOP` kconfig.
This patch helps cse_final_ready_to_boot() and
cse_final_end_of_firmware() function for being meaningful with its
operation and let cse_final() being that outer layer to perform three
operations based on the selected kconfig.
1. send cse eop command
2. perform cse_final_ready_to_boot() operations
3. perform cse_final_end_of_firmware() operations
Additionally, ensures the platform that choose to send EOP late
(like JSL and TGL) is not being impacted due to this code refactoring
hence, skip calling into CSE.final if SoC selects
`SOC_INTEL_CSE_SEND_EOP_LATE` config.
BUG=b:260041679
TEST=Able to send EOP command successfully for Google/Taeko.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I412291c9378011509d3825f9b01e81bfced53303
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69975
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 2cb3452a89..9b8db54efd 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1228,17 +1228,13 @@ static void cse_set_state(struct device *dev) * performed by FSP NotifyPhase(Ready To Boot) API invocations. * * Operations are: - * 1. Send EOP to CSE if not done. - * 2. Perform global reset lock. - * 3. Put HECI1 to D0i3 and disable the HECI1 if the user selects + * 1. Perform global reset lock. + * 2. Put HECI1 to D0i3 and disable the HECI1 if the user selects * DISABLE_HECI1_AT_PRE_BOOT config or CSE HFSTS1 Operation Mode is * `Software Temporary Disable`. */ static void cse_final_ready_to_boot(void) { - if (CONFIG(SOC_INTEL_CSE_SET_EOP)) - cse_send_end_of_post(); - cse_control_global_reset_lock(); if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) || cse_is_hfs1_com_soft_temp_disable()) { @@ -1265,6 +1261,14 @@ static void cse_final_end_of_firmware(void) */ static void cse_final(struct device *dev) { + /* SoC user decided to send EOP late */ + if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) + return; + + /* 1. Send EOP to CSE if not done.*/ + if (CONFIG(SOC_INTEL_CSE_SET_EOP)) + cse_send_end_of_post(); + if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT)) cse_final_ready_to_boot(); |