mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo

Add thermal table settings for tarlo which shares the same firmware with
taeko

BUG=b:215033683
TEST=emerge-brya coreboot

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I37f79cde502115bbf65bb97216eddb6ea22b1648
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

1 files changed, 123 insertions, 1 deletions

diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index b4cda82487..a2838b2730 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -34,6 +34,10 @@ fw_config
 		option BOOT_EMMC_DISABLED		0
 		option BOOT_EMMC_ENABLED		1
 	end
+	field THERMAL 16
+		option THERMAL_FAN_TABLE_0		0
+		option THERMAL_FAN_TABLE_1		1
+	end
 	field HPS 17
 		option HPS_ABSENT			0
 		option HPS_PRESENT			1
@@ -238,7 +242,125 @@ chip soc/intel/alderlake
 				register "options.fan.fine_grained_control" = "1"
 				register "options.fan.step_size" = "2"
 
-				device generic 0 alias dptf_policy on end
+				device generic 0 on
+					probe THERMAL THERMAL_FAN_TABLE_0
+				end
+			end
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""DRAM_SOC""
+				register "options.tsr[1].desc" = ""Ambient""
+				register "options.tsr[2].desc" = ""Charger""
+				register "options.tsr[3].desc" = ""WWAN""
+
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {
+						.target = DPTF_CPU,
+						.thresholds = {
+								TEMP_PCT(85, 90),
+								TEMP_PCT(80, 74),
+								TEMP_PCT(75, 74),
+								TEMP_PCT(70, 74),
+								TEMP_PCT(65, 74),
+						}
+					},
+					[1] = {
+						.target = DPTF_TEMP_SENSOR_1,
+						.thresholds = {
+								TEMP_PCT(57, 70),
+								TEMP_PCT(54, 60),
+								TEMP_PCT(48, 60),
+								TEMP_PCT(45, 45),
+								TEMP_PCT(42, 39),
+						}
+					},
+					[2] = {
+						.target = DPTF_TEMP_SENSOR_2,
+						.thresholds = {
+								TEMP_PCT(57, 70),
+								TEMP_PCT(54, 50),
+								TEMP_PCT(48, 60),
+								TEMP_PCT(45, 45),
+								TEMP_PCT(42, 39),
+						}
+					},
+					[3] = {
+						.target = DPTF_TEMP_SENSOR_3,
+						.thresholds = {
+								TEMP_PCT(57, 70),
+								TEMP_PCT(54, 60),
+								TEMP_PCT(48, 60),
+								TEMP_PCT(45, 45),
+								TEMP_PCT(42, 39),
+						}
+					}
+				}"
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 90, 6000),
+					[2] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_1, 90, 6000),
+					[3] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_2, 90, 6000),
+					[4] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_3, 90, 6000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,     100, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,     100, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,     100, SHUTDOWN),
+					[4] = DPTF_CRITICAL(TEMP_SENSOR_3,     100, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 15000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+					.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = { 100, 6000, 220, 2200, },
+					[1] = {  92, 5500, 180, 1800, },
+					[2] = {  85, 5000, 145, 1450, },
+					[3] = {  70, 4400, 115, 1150, },
+					[4] = {  56, 3900,  90,  900, },
+					[5] = {  45, 3300,  55,  550, },
+					[6] = {  38, 3000,  30,  300, },
+					[7] = {  33, 2900,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 1 on
+					probe THERMAL THERMAL_FAN_TABLE_1
+				end
 			end
 		end
 		device ref pcie4_0 on