soc/intel/skylake: Enable SA IMGU depending on devicetree configuration

Currently, SA IMGU gets enabled by the option SaImguEnable,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SA IMGU controller.

All corresponding mainboards were checked if the devicetree
configuration matches the SaImguEnable setting, and missing entries
were added.

Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner

12 files changed, 13 insertions, 12 deletions

diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index f6c42f1a94..bede4e325e 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -39,7 +39,6 @@ chip soc/intel/skylake
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
-	register "SaImguEnable" = "0"
 	register "Cio2Enable" = "0"
 	register "PmTimerDisabled" = "1"
 	register "HeciEnabled" = "0"
@@ -239,6 +238,7 @@ chip soc/intel/skylake
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on  end # Thermal Subsystem
+		device pci 05.0 off end # SA IMGU
 		device pci 08.0 on  end # Gaussian Mixture Model
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 73f8281d64..94861473b9 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -49,7 +49,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "1"
-	register "SaImguEnable" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -247,6 +246,7 @@ chip soc/intel/skylake
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on  end # SA thermal subsystem
+		device pci 05.0 on  end # SA IMGU
 		device pci 13.0 off end # Integrated Sensor Hub
 		device pci 14.0 on
 			chip drivers/usb/acpi
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 8c638bad0c..e672940f3c 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -39,7 +39,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "1"
-	register "SaImguEnable" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -267,6 +266,7 @@ chip soc/intel/skylake
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on  end # SA thermal subsystem
+		device pci 05.0 on  end # SA IMGU
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 851e240ddb..7ee311699b 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -38,7 +38,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "0"
-	register "SaImguEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -282,6 +281,7 @@ chip soc/intel/skylake
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on  end # SA thermal subsystem
+		device pci 05.0 off end # SA IMGU
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index e4f31123b5..c454348672 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -39,7 +39,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "1"
-	register "SaImguEnable" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -288,6 +287,7 @@ chip soc/intel/skylake
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on  end # SA thermal subsystem
+		device pci 05.0 on  end # SA IMGU
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index c7540e95ac..aef571a9fc 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -44,7 +44,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "1"
-	register "SaImguEnable" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -267,6 +266,7 @@ chip soc/intel/skylake
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on  end # SA thermal subsystem
+		device pci 05.0 on  end # SA IMGU
 		device pci 14.0 on
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 0c221af2d2..d21f98474a 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -49,7 +49,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "0"
-	register "SaImguEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -246,6 +245,7 @@ chip soc/intel/skylake
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on  end # SA thermal subsystem
+		device pci 05.0 off end # SA IMGU
 		device pci 14.0 on
 			chip drivers/usb/acpi
 				register "desc" = ""Root Hub""
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index af501561af..64ef501536 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -39,7 +39,6 @@ chip soc/intel/skylake
 	register "IoBufferOwnership" = "3"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "1"
-	register "SaImguEnable" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "PttSwitch" = "0"
 	register "SkipExtGfxScan" = "1"
@@ -268,6 +267,7 @@ chip soc/intel/skylake
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on  end # SA thermal subsystem
+		device pci 05.0 on  end # SA IMGU
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index ea3d814e20..fe5edbe9b9 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -10,7 +10,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "PmTimerDisabled" = "1"
 	register "Cio2Enable" = "1"
-	register "SaImguEnable" = "1"
 
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+
@@ -121,6 +120,7 @@ chip soc/intel/skylake
 	}"
 
 	device domain 0 on
+		device pci 05.0 on  end # SA IMGU
 		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
 		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
 		device pci 1c.5 on  end # PCI Express Port 6 x1 SLOT3
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index 63861c616f..f0759efa90 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -45,7 +45,6 @@ chip soc/intel/skylake
 	register "HeciEnabled" = "1"
 	register "PmTimerDisabled" = "1"
 	register "SaGv" = "SaGv_Enabled"
-	register "SaImguEnable" = "0"
 	register "IslVrCmd" = "2"
 	register "PmConfigSlpS3MinAssert" = "2"		# 50ms
 	register "PmConfigSlpS4MinAssert" = "4"		# 4s
@@ -218,6 +217,7 @@ chip soc/intel/skylake
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 off end # SA thermal subsystem
+		device pci 05.0 off end # SA IMGU
 		device pci 08.0 off end # Gaussian Mixture Model
 		device pci 13.0 off end # Integrated Sensor Hub
 		device pci 14.0 on  end # USB xHCI
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index cb0d2fc4ac..80e89f6cce 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -230,7 +230,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	       sizeof(params->SerialIoDevMode));
 
 	params->PchCio2Enable = config->Cio2Enable;
-	params->SaImguEnable = config->SaImguEnable;
+
+	dev = pcidev_path_on_root(SA_DEVFN_IMGU);
+	params->SaImguEnable = dev && dev->enabled;
 
 	dev = pcidev_path_on_root(PCH_DEVFN_CSE_3);
 	params->Heci3Enabled = dev ? dev->enabled : 0;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 404a9f417e..33fe52c2b6 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -302,7 +302,6 @@ struct soc_intel_skylake_config {
 
 	/* Camera */
 	u8 Cio2Enable;
-	u8 SaImguEnable;
 
 	/* eMMC and SD */
 	u8 ScsEmmcHs400Enabled;