diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2021-07-02 10:05:09 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-05 10:48:41 +0000 |
commit | 4d06ff0faaae792801c1a104e3769e69e97ef457 (patch) | |
tree | 1e29d854ddc6a93572ea64a00d1c9fce54a509dd | |
parent | 2aeb2a1561d5a2316d84d476a4089783c6bd98db (diff) |
nb/intel/x4x: Use write32p and read32p
This removes the need for type conversions all over the place.
Change-Id: I633a453aff17f1cbbe06b60e3efb67661733d06c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56029
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r-- | src/northbridge/intel/x4x/dq_dqs.c | 20 | ||||
-rw-r--r-- | src/northbridge/intel/x4x/raminit_ddr23.c | 4 | ||||
-rw-r--r-- | src/northbridge/intel/x4x/rcven.c | 2 |
3 files changed, 13 insertions, 13 deletions
diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index cda503ec3b..e4cc888875 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -170,13 +170,13 @@ static u8 test_dq_aligned(const struct sysinfo *s, const u8 channel) if ((count1 % 16) == 0) mchbar_write32(0xf90, 1); const u32 pattern = write_training_schedule[count1]; - write32((u32 *)(uintptr_t)address + 8 * count1, pattern); - write32((u32 *)(uintptr_t)address + 8 * count1 + 4, pattern); + write32p(address + 8 * count1, pattern); + write32p(address + 8 * count1 + 4, pattern); } const u32 good = write_training_schedule[count]; - write32(&data[0], read32((u32 *)(uintptr_t)address + 8 * count)); - write32(&data[4], read32((u32 *)(uintptr_t)address + 8 * count + 4)); + write32(&data[0], read32p(address + 8 * count)); + write32(&data[4], read32p(address + 8 * count + 4)); FOR_EACH_BYTELANE(lane) { u8 expected = (good >> ((lane % 4) * 8)) & 0xff; if (data[lane] != expected) @@ -353,8 +353,8 @@ static u8 test_dqs_aligned(const struct sysinfo *s, const u8 channel) address = test_address(channel, rank); for (i = 0; i < RT_PATTERN_SIZE; i++) { const u32 good = read_training_schedule[i]; - write32(&data[0], read32((u32 *)(uintptr_t)address + i * 8)); - write32(&data[4], read32((u32 *)(uintptr_t)address + i * 8 + 4)); + write32(&data[0], read32p(address + i * 8)); + write32(&data[4], read32p(address + i * 8 + 4)); FOR_EACH_BYTELANE(lane) { if (data[lane] != (good & 0xff)) @@ -442,8 +442,8 @@ int do_read_training(struct sysinfo *s) address = test_address(channel, rank); for (i = 0; i < RT_PATTERN_SIZE; i++) { content = read_training_schedule[i]; - write32((u32 *)(uintptr_t)address + 8 * i, content); - write32((u32 *)(uintptr_t)address + 8 * i + 4, content); + write32p(address + 8 * i, content); + write32p(address + 8 * i + 4, content); } } @@ -617,8 +617,8 @@ static void sample_dq(const struct sysinfo *s, u8 channel, u8 rank, memset(high_found, 0, TOTAL_BYTELANES * sizeof(high_found[0])); for (samples = 0; samples < N_SAMPLES; samples++) { - write32((u32 *)(uintptr_t)address, 0x12341234); - write32((u32 *)(uintptr_t)address + 4, 0x12341234); + write32p(address, 0x12341234); + write32p(address + 4, 0x12341234); udelay(5); FOR_EACH_BYTELANE(lane) { u8 dq_high = (mchbar_read8(0x561 + 0x400 * channel diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 126a44bfcd..d19a83af87 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1283,7 +1283,7 @@ void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val) } data32 <<= 3; - read32((void *)(uintptr_t)(data32 | addr)); + read32p(data32 | addr); udelay(10); mchbar_clrsetbits8(0x271, 0x3e, NORMALOP_CMD); mchbar_clrsetbits8(0x671, 0x3e, NORMALOP_CMD); @@ -2090,7 +2090,7 @@ void do_raminit(struct sysinfo *s, int fast_boot) if (s->boot_path == BOOT_PATH_NORMAL) { FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { for (bank = 0; bank < 4; bank++) - read32((u32 *)(uintptr_t)(test_address(ch, r) | 0x800000 | (bank << 12))); + read32p(test_address(ch, r) | 0x800000 | (bank << 12)); } } printk(BIOS_DEBUG, "Done dummy reads\n"); diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 5bb395a518..1f8be79938 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -38,7 +38,7 @@ static u8 sampledqs(u32 addr, u8 lane, u8 channel) } mfence(); /* Read strobe */ - read32((void *)(uintptr_t)addr); + read32p(addr); mfence(); return mchbar_read8(sample_offset) >> 6 & 1; } |