diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2021-09-24 18:33:38 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-01 16:01:49 +0000 |
| commit | 4bb63e81f29067341995727eabf81750657f32c7 (patch) | |
| tree | 8a796f6b80bea16f8309c90de2e67dc9f9c52665 | |
| parent | ae90f2ebc5f48acb72d66fc7433dcad0c7e367df (diff) | |
soc/intel/common: Add PMC IPC commands for FIVR control
Add PMC IPC commands information for FIVR control functionality
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I9d08bb71f7ea5da7614c68fc0ce4edf9aef59baa
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/pmc_ipc.h | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h index 735438b8c8..1877fe43fb 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h @@ -18,12 +18,20 @@ /* IPC command to control FIVR Configuration */ #define PMC_IPC_CMD_COMMAND_FIVR 0xA3 +/* IPC subcommand to read FIVR Register */ +#define PMC_IPC_CMD_CMD_ID_FIVR_READ 0x00 /* IPC subcommand to write FIVR Register */ #define PMC_IPC_CMD_CMD_ID_FIVR_WRITE 0x01 /* IPC subcommand to control RFI Control 0 register logic write */ -#define PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC 0x00 +#define PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC 0 /* IPC subcommand to control RFI Control 4 register logic write */ -#define PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC 0x01 +#define PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC 1 +/* IPC subcommand to control EMI Control 0 register logic write */ +#define PMC_IPC_SUBCMD_EMI_CTRL0_LOGIC 2 +/* IPC subcommand to control FFFC_FAULT_STATUS register logic read */ +#define PMC_IPC_SUBCMD_FFFC_FAULT_STATUS 3 +/* IPC subcommand to control FFFC_RFI_STATUS register logic read */ +#define PMC_IPC_SUBCMD_FFFC_RFI_STATUS 4 #define PMC_IPC_CMD_FIELD(name, val) \ ((((val) & PMC_IPC_CMD_##name##_MASK) << PMC_IPC_CMD_##name##_SHIFT)) |