soc/intel/alderlake: Fix PCI IRQ tables

Both the IO-APIC and PIC mode PCI IRQ tables are incorrect for ADL; the
2nd field in each package is supposed to be pin, not function number,
and some of the IRQ #s differ from what the FSP programs, therefore
align the ACPI table to match what the FSP is currently programming.

BUG=b:180105941
TEST=boot brya, no more `GSI INT` or `failed to derive IRQ routing`
errors seen in dmesg

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I182be69e8d9ebd854ed74dbb69f4d1f1a539cf2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

2 files changed, 39 insertions, 48 deletions

diff --git a/src/soc/intel/alderlake/acpi/pci_irqs.asl b/src/soc/intel/alderlake/acpi/pci_irqs.asl
index 49e452f12b..3fdd0775ed 100644
--- a/src/soc/intel/alderlake/acpi/pci_irqs.asl
+++ b/src/soc/intel/alderlake/acpi/pci_irqs.asl
@@ -2,10 +2,8 @@
 #include <soc/irq.h>
 
 Name (PICP, Package () {
-	/* D31: HDA, SMBUS, TRACEHUB */
-	Package(){0x001FFFFF, 3, 0, HDA_IRQ },
-	Package(){0x001FFFFF, 4, 0, SMBUS_IRQ },
-	Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ },
+	/* D31: HDA, SMBus, TraceHub, GbE */
+	Package(){0x001FFFFF, 0, 0, TRACEHUB_IRQ },
 	/* D30: UART0, UART1, SPI0, SPI1 */
 	Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
 	Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
@@ -17,14 +15,10 @@ Name (PICP, Package () {
 	Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
 	Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
 	/* D28: RP1 ~ RP8 */
-	Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
-	Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
-	Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
-	Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
-	Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
-	Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
-	Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
-	Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
+	Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, /* RP 1 and 5 */
+	Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, /* RP 2 and 6 */
+	Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, /* RP 3 and 7 */
+	Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, /* RP 4 and 8 */
 	/* D25: I2C4, I2C5, UART2 */
 	Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
 	Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
@@ -34,8 +28,8 @@ Name (PICP, Package () {
 	/* D22: CSME */
 	Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
 	Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
-	Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
-	Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
+	Package(){0x0016FFFF, 2, 0, CSME_IDE_IRQ },
+	Package(){0x0016FFFF, 3, 0, CSME_KT_IRQ },
 	/* D21: I2C0 ~ I2C3 */
 	Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
 	Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
@@ -44,19 +38,17 @@ Name (PICP, Package () {
 	/* D20: xHCI, xDCI, SRAM, CNVI_WIFI */
 	Package(){0x0014FFFF, 0, 0, xHCI_IRQ },
 	Package(){0x0014FFFF, 1, 0, xDCI_IRQ },
-	Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ },
-	/* D19: SPI3 */
-	Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ },
 	/* D18: ISH, SPI2 */
 	Package(){0x0012FFFF, 0, 0, ISH_IRQ },
-	Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
-	/* D16: CNVI_BT, TCH0, TCH1 */
-	Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ },
-	Package(){0x0010FFFF, 6, 0, THC0_IRQ },
-	Package(){0x0010FFFF, 7, 0, THC1_IRQ },
+	Package(){0x0012FFFF, 1, 0, LPSS_SPI2_IRQ },
+	/* D17: UART3 */
+	Package(){0x0011FFFF, 0, 0, LPSS_UART3_IRQ },
+	/* D16: THC0, THC1 */
+	Package(){0x0010FFFF, 0, 0, THC0_IRQ },
+	Package(){0x0010FFFF, 1, 0, THC1_IRQ },
 	/* D13: xHCI, xDCI */
-	Package(){0x000DFFFF, 0, 0, xHCI_IRQ },
-	Package(){0x000DFFFF, 1, 0, xDCI_IRQ },
+	Package(){0x000DFFFF, 0, 0, CPU_xHCI_IRQ },
+	Package(){0x000DFFFF, 1, 0, CPU_xDCI_IRQ },
 	/* D8: GNA */
 	Package(){0x0008FFFF, 0, 0, GNA_IRQ },
 	/* D7: TBT PCIe */
@@ -76,9 +68,10 @@ Name (PICP, Package () {
 
 Name (PICN, Package () {
 	/* D31: HDA, SMBUS, TRACEHUB */
+	Package(){0x001FFFFF, 0, 0, 11 },
+	Package(){0x001FFFFF, 1, 0, 10 },
+	Package(){0x001FFFFF, 2, 0, 11 },
 	Package(){0x001FFFFF, 3, 0, 11 },
-	Package(){0x001FFFFF, 4, 0, 11 },
-	Package(){0x001FFFFF, 7, 0, 11 },
 	/* D30: UART0, UART1, SPI0, SPI1 */
 	Package(){0x001EFFFF, 0, 0, 11 },
 	Package(){0x001EFFFF, 1, 0, 10 },
@@ -94,10 +87,6 @@ Name (PICN, Package () {
 	Package(){0x001CFFFF, 1, 0, 10 },
 	Package(){0x001CFFFF, 2, 0, 11 },
 	Package(){0x001CFFFF, 3, 0, 11 },
-	Package(){0x001CFFFF, 4, 0, 11 },
-	Package(){0x001CFFFF, 5, 0, 10 },
-	Package(){0x001CFFFF, 6, 0, 11 },
-	Package(){0x001CFFFF, 7, 0, 11 },
 	/* D25: I2C4, I2C5, UART2 */
 	Package(){0x0019FFFF, 0, 0, 11 },
 	Package(){0x0019FFFF, 1, 0, 10 },
@@ -107,26 +96,27 @@ Name (PICN, Package () {
 	/* D22: CSME */
 	Package(){0x0016FFFF, 0, 0, 11 },
 	Package(){0x0016FFFF, 1, 0, 10 },
-	Package(){0x0016FFFF, 4, 0, 11 },
-	Package(){0x0016FFFF, 5, 0, 10 },
+	Package(){0x0016FFFF, 2, 0, 11 },
+	Package(){0x0016FFFF, 3, 0, 11 },
 	/* D21: I2C0 ~ I2C3 */
 	Package(){0x0015FFFF, 0, 0, 11 },
 	Package(){0x0015FFFF, 1, 0, 10 },
 	Package(){0x0015FFFF, 2, 0, 11 },
 	Package(){0x0015FFFF, 3, 0, 11 },
-	/* D20: xHCI, xDCI, CNVI_WIFI */
+	/* D20: xHCI, xDCI, SRAM, CNVI_WIFI */
 	Package(){0x0014FFFF, 0, 0, 11 },
 	Package(){0x0014FFFF, 1, 0, 10 },
-	Package(){0x0014FFFF, 3, 0, 11 },
+	Package(){0x0014FFFF, 2, 0, 11 },
 	/* D19: SPI3 */
 	Package(){0x0013FFFF, 0, 0, 11 },
 	/* D18: ISH, SPI2 */
 	Package(){0x0012FFFF, 0, 0, 11 },
-	Package(){0x0012FFFF, 6, 0, 11 },
-	/* D16: CNVI_BT, TCH0, TCH1 */
-	Package(){0x0010FFFF, 2, 0, 11 },
-	Package(){0x0010FFFF, 6, 0, 11 },
-	Package(){0x0010FFFF, 7, 0, 11 },
+	Package(){0x0012FFFF, 1, 0, 10 },
+	/* D17: UART3 */
+	Package(){0x0011FFFF, 0, 0, 11 },
+	/* D16: THC0, THC1 */
+	Package(){0x0010FFFF, 0, 0, 11 },
+	Package(){0x0010FFFF, 1, 0, 10 },
 	/* D13: xHCI, xDCI */
 	Package(){0x000DFFFF, 0, 0, 11 },
 	Package(){0x000DFFFF, 1, 0, 10 },
diff --git a/src/soc/intel/alderlake/include/soc/irq.h b/src/soc/intel/alderlake/include/soc/irq.h
index 98e3f42108..9d471fd90b 100644
--- a/src/soc/intel/alderlake/include/soc/irq.h
+++ b/src/soc/intel/alderlake/include/soc/irq.h
@@ -17,15 +17,13 @@
 #define LPSS_I2C5_IRQ	32
 #define LPSS_SPI0_IRQ	36
 #define LPSS_SPI1_IRQ	37
-#define LPSS_SPI2_IRQ	34
-#define LPSS_SPI3_IRQ	43
+#define LPSS_SPI2_IRQ	39
 
 #define LPSS_UART0_IRQ	16
 #define LPSS_UART1_IRQ	17
 #define LPSS_UART2_IRQ	33
+#define LPSS_UART3_IRQ	25
 
-#define HDA_IRQ		16
-#define SMBUS_IRQ	16
 #define TRACEHUB_IRQ	16
 
 #define PCIE_1_IRQ	16
@@ -45,14 +43,14 @@
 
 #define xHCI_IRQ	16
 #define xDCI_IRQ	17
-#define CNVI_WIFI_IRQ	16
-
-#define CNVI_BT_IRQ	18
 
 #define THC0_IRQ	23
-#define THC1_IRQ	24
+#define THC1_IRQ	22
+
+#define ISH_IRQ		26
 
-#define ISH_IRQ		16
+#define CPU_xHCI_IRQ	16
+#define CPU_xDCI_IRQ	17
 
 #define TBT_PCIe0_IRQ	16
 #define TBT_PCIe1_IRQ	17
@@ -61,6 +59,8 @@
 
 #define HECI_1_IRQ	16
 #define HECI_2_IRQ	17
+#define CSME_IDE_IRQ	18
+#define CSME_KT_IRQ	19
 #define HECI_3_IRQ	16
 #define HECI_4_IRQ	19
 
@@ -69,4 +69,5 @@
 #define THERMAL_IRQ	16
 #define IPU_IRQ		16
 #define GNA_IRQ		16
+
 #endif