diff options
| author | Xavi Drudis Ferran <xdrudis@tinet.cat> | 2010-08-22 19:54:26 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-08-22 19:54:26 +0000 |
| commit | 4793ef1f824a2143443c5e2fe63b44deaae7dba7 (patch) | |
| tree | 24b84ede5519acf3cec3a63c52d94b9a90001409 | |
| parent | 213ab94ea4bd23f4b5f2b00a09a535925fe2c6a6 (diff) | |
documented workaround erratum 414, see
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010
with patch.erratum414 it stops here (next patches don't make it get further,
but they're needed according to documentation, don't break anything for me and
I still don't have a solution for booting, so I'm keeping them there in case
they fix something.
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Loading stage image.
Check CBFS header at fffffd2e
magic is 4f524243
Found CBFS header at fffffd2e
Check fallback/romstage
CBFS: follow chain: fff00000 + 38 + 15b41 + align -> fff15b80
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x200000 (1114112 bytes), entry @
0x20000
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/wrappers/mcti_d.c | 18 |
2 files changed, 20 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index a30ac7b911..0de0a0bd42 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -118,6 +118,7 @@ #define TestFail 2 /* func 2, offset 40h-5C, bit 2*/ #define DqsRcvEnTrain 18 /* func 2, offset 78h, bit 18*/ #define EnDramInit 31 /* func 2, offset 7Ch, bit 31*/ +#define PchgPDModeSel 23 /* func 2, offset 84h, bit 23 */ #define DisAutoRefresh 18 /* func 2, offset 8Ch, bit 18*/ #define InitDram 0 /* func 2, offset 90h, bit 0*/ #define BurstLength32 10 /* func 2, offset 90h, bit 10*/ @@ -128,6 +129,7 @@ #define MemClkFreqVal 3 /* func 2, offset 94h, bit 3*/ #define RDqsEn 12 /* func 2, offset 94h, bit 12*/ #define DisDramInterface 14 /* func 2, offset 94h, bit 14*/ +#define PowerDownEn 15 /* func 2, offset 94h, bit 15*/ #define DctAccessWrite 30 /* func 2, offset 98h, bit 30*/ #define DctAccessDone 31 /* func 2, offset 98h, bit 31*/ #define MemClrStatus 0 /* func 2, offset A0h, bit 0*/ diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index f6c44c500b..61b432304c 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -415,6 +415,23 @@ static void vErratum372(struct DCTStatStruc *pDCTstat) wrmsr(NB_CFG_MSR, msr); } } + +static void vErratum414(struct DCTStatStruc *pDCTstat) +{ + int dct=0; + for(; dct < 2 ; dct++) + { + int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct)); + int powerDown = dRAMConfigHi && (1 << PowerDownEn ) ; + int ddr3 = dRAMConfigHi && (1 << Ddr3Mode ) ; + int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct)); + int pchgPDModeSel = dRAMMRS && (1 << PchgPDModeSel ) ; + if (powerDown && ddr3 && pchgPDModeSel ) + { + Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) ); + } + } +} #endif @@ -425,6 +442,7 @@ static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTSt if (pDCTstatA->LogicalCPUID & AMD_DRBH_Cx) { vErrata350(pMCTstat, pDCTstatA); vErratum372(pDCTstatA); + vErratum414(pDCTstatA); } #endif } |