diff options
| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2022-01-04 15:46:15 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-14 14:29:06 +0000 |
| commit | 4503a0cb0fd93928361c45181fedf9266d594f9d (patch) | |
| tree | 3f05ae863915df9ebc40f9a369173619f22f1e3b | |
| parent | a92589bc5c403f1633dc87a5fa9d38836db131dc (diff) | |
mb/google/brya0: Enable CNVi DDR RFIM for brya0 variant
DDR interfaces emit electromagnetic radiation which can couple to the
antennas of various radios that are integrated in the system, and cause
radio frequency interference (RFI). The DDR Radio Frequency Interference
Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband
RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and
ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables
CNVI DDR RFIM feature for brya0 variant.
Refer to Intel doc:640438 and doc:690608 for more details.
BUG=b:201724512
BRANCH=None
TEST=Build and boot with debug FSP and verify CnviDdrRfim UPD value.
Change-Id: I6ad826d0039e400f219c2d407c51762c1751a909
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/brya0/overridetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index cae22572b6..1ef90bc764 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -45,6 +45,9 @@ chip soc/intel/alderlake register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + # Enable CNVi DDR RFIM + register "CnviDdrRfim" = "1" + # FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. register "ext_fivr_settings" = "{ |