AMD amdfam10: Drop EXT_CONF_SUPPORT

Only used for AMD K8 siemens/sitemp_g1p1 with southbridge rs690.

Change-Id: Ie98a77ce190b1bd35996c7f25da0a0fe9819c9c3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7809
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

8 files changed, 70 insertions, 409 deletions

diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig
index 8c260ea6bc..2c56ea7912 100644
--- a/src/cpu/amd/socket_AM2r2/Kconfig
+++ b/src/cpu/amd/socket_AM2r2/Kconfig
@@ -15,10 +15,6 @@ config EXT_RT_TBL_SUPPORT
 	bool
 	default n
 
-config EXT_CONF_SUPPORT
-	bool
-	default n
-
 config CBB
 	hex
 	default 0x0
diff --git a/src/cpu/amd/socket_AM3/Kconfig b/src/cpu/amd/socket_AM3/Kconfig
index 3c7433fe00..48dba03009 100644
--- a/src/cpu/amd/socket_AM3/Kconfig
+++ b/src/cpu/amd/socket_AM3/Kconfig
@@ -15,10 +15,6 @@ config EXT_RT_TBL_SUPPORT
 	bool
 	default n
 
-config EXT_CONF_SUPPORT
-	bool
-	default n
-
 config CBB
 	hex
 	default 0x0
diff --git a/src/cpu/amd/socket_ASB2/Kconfig b/src/cpu/amd/socket_ASB2/Kconfig
index 167cf2fb05..eb2bdc8a63 100644
--- a/src/cpu/amd/socket_ASB2/Kconfig
+++ b/src/cpu/amd/socket_ASB2/Kconfig
@@ -15,10 +15,6 @@ config EXT_RT_TBL_SUPPORT
 	bool
 	default n
 
-config EXT_CONF_SUPPORT
-	bool
-	default n
-
 config CBB
 	hex
 	default 0x0
diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig
index 615387c902..05da489bf5 100644
--- a/src/cpu/amd/socket_C32/Kconfig
+++ b/src/cpu/amd/socket_C32/Kconfig
@@ -15,10 +15,6 @@ config EXT_RT_TBL_SUPPORT
 	bool
 	default n
 
-config EXT_CONF_SUPPORT
-	bool
-	default n
-
 config CBB
 	hex
 	default 0x0
diff --git a/src/cpu/amd/socket_F_1207/Kconfig b/src/cpu/amd/socket_F_1207/Kconfig
index a69a65af57..c21ef556d7 100644
--- a/src/cpu/amd/socket_F_1207/Kconfig
+++ b/src/cpu/amd/socket_F_1207/Kconfig
@@ -14,10 +14,6 @@ config EXT_RT_TBL_SUPPORT
 	bool
 	default n
 
-config EXT_CONF_SUPPORT
-	bool
-	default n
-
 config CBB
 	hex
 	default 0x0
diff --git a/src/northbridge/amd/amdfam10/conf.c b/src/northbridge/amd/amdfam10/conf.c
index 4dc8480413..6688e0addb 100644
--- a/src/northbridge/amd/amdfam10/conf.c
+++ b/src/northbridge/amd/amdfam10/conf.c
@@ -38,13 +38,6 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
 	dev = __f1_dev[0];
 #endif
 
-#if CONFIG_EXT_CONF_SUPPORT
-	// I will use ext space only for simple
-	pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8]
-	d.mask = pci_read_config32(dev, 0x114);  // enable is bit 0
-	pci_write_config32(dev, 0x110, nodeid | (0<<28));
-	d.base = pci_read_config32(dev, 0x114) & 0x1fffff00; //[47:27] at [28:8];
-#else
 	u32 temp;
 	temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
 	d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out  DramMask [26:24] too
@@ -57,7 +50,6 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
 	d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
 	temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
 	d.base |= temp<<21;
-#endif
 	return d;
 }
 
@@ -66,15 +58,6 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
 {
 	u32 i;
 	device_t dev;
-#if CONFIG_EXT_CONF_SUPPORT
-	// I will use ext space only for simple
-	u32 d_base_i, d_base_d, d_mask_i, d_mask_d;
-	d_base_i = nodeid | (0<<28);
-	d_base_d = d.base | nodeid; //[47:27] at [28:8];
-	d_mask_i = nodeid | (1<<28); // [47:27] at [28:8]
-	d_mask_d = d.mask;  // enable is bit 0
-
-#else
 	u32 d_base_lo, d_base_hi, d_mask_lo, d_mask_hi;
 	u32 d_base_lo_reg, d_base_hi_reg, d_mask_lo_reg, d_mask_hi_reg;
 	d_mask_lo =  (((d.mask<<(8+3))|(0x07<<16)) & 0xffff0000)|nodeid; // need to fill DramMask[26:24] with ones
@@ -86,7 +69,6 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
 	d_mask_hi_reg = 0x144+(nodeid<<3);
 	d_base_lo_reg = 0x40+(nodeid<<3);
 	d_base_hi_reg = 0x140+(nodeid<<3);
-#endif
 
 	for (i=0;i<nodes;i++) {
 #if defined(__PRE_RAM__)
@@ -94,19 +76,10 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
 #else
 		dev = __f1_dev[i];
 #endif
-
-#if CONFIG_EXT_CONF_SUPPORT
-		// I will use ext space only for simple
-		pci_write_config32(dev, 0x110, d_base_i);
-		pci_write_config32(dev, 0x114, d_base_d); //[47:27] at [28:8];
-		pci_write_config32(dev, 0x110, d_mask_i); // [47:27] at [28:8]
-		pci_write_config32(dev, 0x114, d_mask_d);  // enable is bit 0
-#else
 		pci_write_config32(dev, d_mask_lo_reg, d_mask_lo); // need to fill DramMask[26:24] with ones
 		pci_write_config32(dev, d_mask_hi_reg, d_mask_hi);
 		pci_write_config32(dev, d_base_lo_reg, d_base_lo);
 		pci_write_config32(dev, d_base_hi_reg, d_base_hi);
-#endif
 	}
 
 #if defined(__PRE_RAM__)
@@ -321,67 +294,6 @@ static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes)
 #endif // CONFIG_AMDMCT
 
 
-#if CONFIG_EXT_CONF_SUPPORT
-static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest,
-						u32 busn_min, u32 busn_max,
-						u32 type)
-{
-	device_t dev;
-	u32 i;
-	u32 tempreg;
-	u32 index_min, index_max;
-	u32 dest_min, dest_max;
-	index_min = busn_min>>2; dest_min = busn_min - (index_min<<2);
-	index_max = busn_max>>2; dest_max = busn_max - (index_max<<2);
-
-	// three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
-#if defined(__PRE_RAM__)
-	dev = NODE_PCI(nodeid, 1);
-#else
-	dev = __f1_dev[nodeid];
-#endif
-	if (index_min== index_max) {
-		pci_write_config32(dev, 0x110, index_min | (type<<28));
-		tempreg = pci_read_config32(dev, 0x114);
-		for (i=dest_min; i<=dest_max; i++) {
-			tempreg &= ~(0xff<<(i*8));
-			tempreg |= (cfg_map_dest<<(i*8));
-		}
-		pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
-		pci_write_config32(dev, 0x114, tempreg);
-	} else if (index_min<index_max) {
-		pci_write_config32(dev, 0x110, index_min | (type<<28));
-		tempreg = pci_read_config32(dev, 0x114);
-		for (i=dest_min; i<=3; i++) {
-			tempreg &= ~(0xff<<(i*8));
-			tempreg |= (cfg_map_dest<<(i*8));
-		}
-		pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
-		pci_write_config32(dev, 0x114, tempreg);
-
-		pci_write_config32(dev, 0x110, index_max | (type<<28));
-		tempreg = pci_read_config32(dev, 0x114);
-		for (i=0; i<=dest_max; i++) {
-			tempreg &= ~(0xff<<(i*8));
-			tempreg |= (cfg_map_dest<<(i*8));
-		}
-		pci_write_config32(dev, 0x110, index_max | (type<<28)); // do i need to write it again
-		pci_write_config32(dev, 0x114, tempreg);
-		if ((index_max-index_min)>1) {
-			tempreg = 0;
-			for (i=0; i<=3; i++) {
-				tempreg &= ~(0xff<<(i*8));
-				tempreg |= (cfg_map_dest<<(i*8));
-			}
-			for (i=index_min+1; i<index_max;i++) {
-				pci_write_config32(dev, 0x110, i | (type<<28));
-				pci_write_config32(dev, 0x114, tempreg);
-			}
-		}
-	}
-}
-#endif
-
 static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
 				u32 busn_min, u32 busn_max, u32 segbit,
 				u32 nodes)
@@ -393,39 +305,15 @@ static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
 	busn_min>>=segbit;
 	busn_max>>=segbit;
 
-#if CONFIG_EXT_CONF_SUPPORT
-	if (ht_c_index < 4) {
-#endif
-		tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24);
-		for (i=0; i<nodes; i++) {
-		#if defined(__PRE_RAM__)
-			dev = NODE_PCI(i, 1);
-		#else
-			dev = __f1_dev[i];
-		#endif
-			pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg);
-		}
-#if CONFIG_EXT_CONF_SUPPORT
-
-		return;
-	}
-
-	// if ht_c_index > 3, We should use extend space x114_x6
-	u32 cfg_map_dest;
-	u32 j;
-
-	// for nodeid at first
-	cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
-
-	set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, busn_min, busn_max, 6);
-
-	// all other nodes
-	cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
-	for (j = 0; j< nodes; j++) {
-		if (j== nodeid) continue;
-		set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, busn_min, busn_max, 6);
+	tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24);
+	for (i=0; i<nodes; i++) {
+	#if defined(__PRE_RAM__)
+		dev = NODE_PCI(i, 1);
+	#else
+		dev = __f1_dev[i];
+	#endif
+		pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg);
 	}
-#endif
 }
 
 static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
@@ -434,33 +322,14 @@ static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
 	u32 i;
 	device_t dev;
 
-#if CONFIG_EXT_CONF_SUPPORT
-	if (ht_c_index<4) {
-#endif
-		for (i=0; i<nodes; i++) {
-		#if defined(__PRE_RAM__)
-			dev = NODE_PCI(i, 1);
-		#else
-			dev = __f1_dev[i];
-		#endif
-			pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
-		}
-#if CONFIG_EXT_CONF_SUPPORT
-		return;
-	}
-
-	// if hc_c_index >3, We should use busn_min and busn_max to clear extend space
-	u32 cfg_map_dest;
-	u32 j;
-
-
-	// all nodes
-	cfg_map_dest = 0;
-	for (j = 0; j< nodes; j++) {
-		set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, busn_min, busn_max, 6);
+	for (i=0; i<nodes; i++) {
+	#if defined(__PRE_RAM__)
+		dev = NODE_PCI(i, 1);
+	#else
+		dev = __f1_dev[i];
+	#endif
+		pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
 	}
-#endif
-
 }
 
 #if CONFIG_PCI_BUS_SEGN_BITS
@@ -493,51 +362,25 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
 	u32 tempreg;
 	device_t dev;
 
-#if CONFIG_EXT_CONF_SUPPORT
-	if (ht_c_index<4) {
-#endif
-		/* io range allocation */
-		tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) |  ((io_max&0xf0)<<(12-4)); //limit
-		for (i=0; i<nodes; i++) {
-		#if defined(__PRE_RAM__)
-			dev = NODE_PCI(i, 1);
-		#else
-			dev = __f1_dev[i];
-		#endif
-			pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg);
-		}
-		tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4));	     //base :ISA and VGA ?
-		for (i=0; i<nodes; i++) {
-		#if defined(__PRE_RAM__)
-			dev = NODE_PCI(i, 1);
-		#else
-			dev = __f1_dev[i];
-		#endif
-			pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);
-		}
-#if CONFIG_EXT_CONF_SUPPORT
-		return;
+	/* io range allocation */
+	tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) |  ((io_max&0xf0)<<(12-4)); //limit
+	for (i=0; i<nodes; i++) {
+	#if defined(__PRE_RAM__)
+		dev = NODE_PCI(i, 1);
+	#else
+		dev = __f1_dev[i];
+	#endif
+		pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg);
 	}
-
-	u32 cfg_map_dest;
-	u32 j;
-
-	// if ht_c_index > 3, We should use extend space
-
-	if (io_min>io_max) return;
-
-	// for nodeid at first
-	cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
-
-	set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
-
-	// all other nodes
-	cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
-	for (j = 0; j< nodes; j++) {
-		if (j== nodeid) continue;
-		set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
+	tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4));	     //base :ISA and VGA ?
+	for (i=0; i<nodes; i++) {
+	#if defined(__PRE_RAM__)
+		dev = NODE_PCI(i, 1);
+	#else
+		dev = __f1_dev[i];
+	#endif
+		pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);
 	}
-#endif
 }
 
 
@@ -546,33 +389,16 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
 {
 	u32 i;
 	device_t dev;
-#if CONFIG_EXT_CONF_SUPPORT
-	if (ht_c_index<4) {
-#endif
-		 /* io range allocation */
-		for (i=0; i<nodes; i++) {
-		#if defined(__PRE_RAM__)
-			dev = NODE_PCI(i, 1);
-		#else
-			dev = __f1_dev[i];
-		#endif
-			pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0);
-			pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0);
-		}
-#if CONFIG_EXT_CONF_SUPPORT
-		return;
-	}
-	// : if hc_c_index > 3, We should use io_min, io_max to clear extend space
-	u32 cfg_map_dest;
-	u32 j;
-
-
-	// all nodes
-	cfg_map_dest = 0;
-	for (j = 0; j< nodes; j++) {
-		set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
+	 /* io range allocation */
+	for (i=0; i<nodes; i++) {
+	#if defined(__PRE_RAM__)
+		dev = NODE_PCI(i, 1);
+	#else
+		dev = __f1_dev[i];
+	#endif
+		pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0);
+		pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0);
 	}
-#endif
 }
 #endif
 
@@ -597,13 +423,6 @@ static void re_set_all_config_map_reg(u32 nodes, u32 segbit,
 			pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
 		}
 	}
-#if CONFIG_EXT_CONF_SUPPORT
-	u32 j;
-	// clear the extend space
-	for (j = 0; j< nodes; j++) {
-		set_addr_map_reg_4_6_in_one_node(j,0, 0, 0xff, 6);
-	}
-#endif
 
 	for (ht_c_index = 1; ht_c_index<sysinfo->ht_c_num; ht_c_index++) {
 		u32 nodeid, linkn;
@@ -717,16 +536,9 @@ static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
 				u32 io_min, u32 io_max)
 {
 	u32 val;
-#if CONFIG_EXT_CONF_SUPPORT
-	if (reg!=0x110) {
-#endif
-		/* io range allocation */
-		index = (reg-0xc0)>>3;
-#if CONFIG_EXT_CONF_SUPPORT
-	} else {
-		index+=4;
-	}
-#endif
+
+	/* io range allocation */
+	index = (reg-0xc0)>>3;
 
 	val = (nodeid & 0x3f); // 6 bits used
 	sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid
@@ -742,16 +554,9 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
 					u32 mmio_min, u32 mmio_max)
 {
 	u32 val;
-#if CONFIG_EXT_CONF_SUPPORT
-	if (reg!=0x110) {
-#endif
-		/* io range allocation */
-		index = (reg-0x80)>>3;
-#if CONFIG_EXT_CONF_SUPPORT
-	} else {
-		index+=8;
-	}
-#endif
+
+	/* io range allocation */
+	index = (reg-0x80)>>3;
 
 	val = (nodeid & 0x3f) ; // 6 bits used
 	sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn
@@ -768,107 +573,40 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
 {
 	u32 i;
 	u32 tempreg;
-#if CONFIG_EXT_CONF_SUPPORT
-	if (reg!=0x110) {
-#endif
-		/* io range allocation */
-		tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) |  ((io_max&0xf0)<<(12-4)); //limit
-		for (i=0; i<sysconf.nodes; i++)
-			pci_write_config32(__f1_dev[i], reg+4, tempreg);
 
-		tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4));	      //base :ISA and VGA ?
+	/* io range allocation */
+	tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) |  ((io_max&0xf0)<<(12-4)); //limit
+	for (i=0; i<sysconf.nodes; i++)
+		pci_write_config32(__f1_dev[i], reg+4, tempreg);
+
+	tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4));	      //base :ISA and VGA ?
 #if 0
-		// FIXME: can we use VGA reg instead?
-		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-			printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
-				__func__, dev_path(dev), link);
-			tempreg |= PCI_IO_BASE_VGA_EN;
-		}
-		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
-			tempreg |= PCI_IO_BASE_NO_ISA;
-		}
-#endif
-		for (i=0; i<sysconf.nodes; i++)
-			pci_write_config32(__f1_dev[i], reg, tempreg);
-#if CONFIG_EXT_CONF_SUPPORT
-		return;
+	// FIXME: can we use VGA reg instead?
+	if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+		printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
+			__func__, dev_path(dev), link);
+		tempreg |= PCI_IO_BASE_VGA_EN;
 	}
-
-	u32 cfg_map_dest;
-	u32 j;
-	// if ht_c_index > 3, We should use extend space
-	if (io_min>io_max) return;
-	// for nodeid at first
-	cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
-
-	set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
-
-	// all other nodes
-	cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
-	for (j = 0; j< sysconf.nodes; j++) {
-		if (j== nodeid) continue;
-		set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
+	if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
+		tempreg |= PCI_IO_BASE_NO_ISA;
 	}
 #endif
+	for (i=0; i<sysconf.nodes; i++)
+		pci_write_config32(__f1_dev[i], reg, tempreg);
 }
 
 static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
 {
 	u32 i;
 	u32 tempreg;
-#if CONFIG_EXT_CONF_SUPPORT
-	if (reg!=0x110) {
-#endif
-		/* io range allocation */
-		tempreg = (nodeid&0xf) | (linkn<<4) |	 (mmio_max&0xffffff00); //limit
-		for (i=0; i<nodes; i++)
-			pci_write_config32(__f1_dev[i], reg+4, tempreg);
-		tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
-		for (i=0; i<sysconf.nodes; i++)
-			pci_write_config32(__f1_dev[i], reg, tempreg);
-#if CONFIG_EXT_CONF_SUPPORT
-		return;
-	}
-
-	device_t dev;
-	u32 j;
-	// if ht_c_index > 3, We should use extend space
-	// for nodeid at first
-	u32 enable;
 
-	if (mmio_min>mmio_max) {
-		return;
-	}
-
-	enable = 1;
-
-	dev = __f1_dev[nodeid];
-	tempreg = ((mmio_min>>3) & 0x1fffff00)| (1<<6) | (linkn<<0);
-	pci_write_config32(dev, 0x110, index | (2<<28));
-	pci_write_config32(dev, 0x114, tempreg);
-
-	tempreg = ((mmio_max>>3) & 0x1fffff00) | enable;
-	pci_write_config32(dev, 0x110, index | (3<<28));
-	pci_write_config32(dev, 0x114, tempreg);
-
-
-	// all other nodes
-	tempreg = ((mmio_min>>3) & 0x1fffff00) | (0<<6) | (nodeid<<0);
-	for (j = 0; j< sysconf.nodes; j++) {
-		if (j== nodeid) continue;
-		dev = __f1_dev[j];
-		pci_write_config32(dev, 0x110, index | (2<<28));
-		pci_write_config32(dev, 0x114, tempreg);
-	}
-
-	tempreg = ((mmio_max>>3) & 0x1fffff00) | enable;
-	for (j = 0; j< sysconf.nodes; j++) {
-		if (j==nodeid) continue;
-		dev = __f1_dev[j];
-		pci_write_config32(dev, 0x110, index | (3<<28));
-		pci_write_config32(dev, 0x114, tempreg);
-	 }
-#endif
+	/* io range allocation */
+	tempreg = (nodeid&0xf) | (linkn<<4) |	 (mmio_max&0xffffff00); //limit
+	for (i=0; i<nodes; i++)
+		pci_write_config32(__f1_dev[i], reg+4, tempreg);
+	tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
+	for (i=0; i<sysconf.nodes; i++)
+		pci_write_config32(__f1_dev[i], reg, tempreg);
 }
 
 #endif
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index b28169ec25..a8a8155f30 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -191,9 +191,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l
 		 */
 		ht_c_index = get_ht_c_index(nodeid, link_num, &sysconf);
 
-#if !CONFIG_EXT_CONF_SUPPORT
 		if(ht_c_index>=4) return max;
-#endif
 
 		/* Set up the primary, secondary and subordinate bus numbers.
 		 * We have no idea how many busses are behind this bridge yet,
@@ -433,13 +431,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
 	resource = amdfam10_find_iopair(dev, nodeid, link);
 	if (resource) {
 		u32 align;
-#if CONFIG_EXT_CONF_SUPPORT
-		if((resource->index & 0x1fff) == 0x1110) { // ext
-			align = 8;
-		}
-		else
-#endif
-			align = log2(HT_IO_HOST_ALIGN);
+		align = log2(HT_IO_HOST_ALIGN);
 		resource->base	= 0;
 		resource->size	= 0;
 		resource->align = align;
@@ -458,13 +450,6 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
 		resource->limit = 0xffffffffffULL;
 		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 		resource->flags |= IORESOURCE_BRIDGE;
-
-#if CONFIG_EXT_CONF_SUPPORT
-		if((resource->index & 0x1fff) == 0x1110) { // ext
-			normalize_resource(resource);
-		}
-#endif
-
 	}
 
 	/* Initialize the memory constraints on the current bus */
@@ -476,11 +461,6 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
 		resource->gran = log2(HT_MEM_HOST_ALIGN);
 		resource->limit = 0xffffffffffULL;
 		resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT
-		if((resource->index & 0x1fff) == 0x1110) { // ext
-			normalize_resource(resource);
-		}
-#endif
 	}
 }
 
@@ -1100,18 +1080,6 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max)
 	for(reg = 0xe0; reg <= 0xec; reg += 4) {
 		f1_write_config32(reg, 0);
 	}
-#if CONFIG_EXT_CONF_SUPPORT
-	// all nodes
-	for(i = 0; i< sysconf.nodes; i++) {
-		int index;
-		for(index = 0; index < 64; index++) {
-			pci_write_config32(__f1_dev[i], 0x110, index | (6<<28));
-			pci_write_config32(__f1_dev[i], 0x114, 0);
-		}
-
-	}
-#endif
-
 
 	for(link = dev->link_list; link; link = link->next) {
 		max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max);
diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c
index b4a44ea33e..cdb663263f 100644
--- a/src/northbridge/amd/amdfam10/reset_test.c
+++ b/src/northbridge/amd/amdfam10/reset_test.c
@@ -127,31 +127,6 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b
 		}
 	}
 
-#if CONFIG_EXT_CONF_SUPPORT
-	// let's check that in extend space
-	// use the nodeid extend space to find out the bus for the linkn
-	u32 tempreg;
-	int i;
-	int j;
-	u32 cfg_map_dest;
-	pci_devfn_t dev;
-
-	cfg_map_dest = (1<<7)|(1<<6)|link;
-
-	// three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
-	dev = NODE_PCI(node, 1);
-	for(j=0; j<64; j++) {
-		pci_io_write_config32(dev, 0x110, j | (6<<28));
-		tempreg = pci_io_read_config32(dev, 0x114);
-		for(i=0; i<=3; i++) {
-			tempreg >>= (i*8);
-			if((tempreg & ((1<<7)|(1<<6)|0x3f)) == cfg_map_dest) {
-				return (i+(j<<2)); //busn_min
-			}
-		}
-	}
-#endif
-
 	return 0;
 }