diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-12-08 10:43:08 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-01-06 16:49:00 +0000 |
| commit | 40c9c8aa8021348e0fd6916b0e06f21398fb42c9 (patch) | |
| tree | d7dce3f047ddfac6e2d707949ac9239654fed8b4 | |
| parent | 8d0e77bbd4145e138ff43951c8543cea2c3dfd50 (diff) | |
soc/intel/alderlake: Add soc_get_cpu_rp_vw_idx() function
The PMC IPC method used to enable/disable PCIe srcclks uses the
LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC
command expects the RP number to be its "virtual wire index"
instead. This new function returns this virtual wire index
for each of the CPU PCIe RPs.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5e9710f0d210396f9306b948d9dce8b847300147
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
| -rw-r--r-- | src/soc/intel/alderlake/pcie_rp.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c index dd0cfbc637..26ce785e8e 100644 --- a/src/soc/intel/alderlake/pcie_rp.c +++ b/src/soc/intel/alderlake/pcie_rp.c @@ -6,6 +6,8 @@ #include <soc/pci_devs.h> #include <soc/pcie.h> +#define CPU_CPIE_VW_IDX_BASE 24 + static const struct pcie_rp_group pch_lp_rp_groups[] = { { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, @@ -91,3 +93,20 @@ enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev) return PCIE_RP_UNKNOWN; } + +int soc_get_cpu_rp_vw_idx(const struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return -1; + + switch (dev->path.pci.devfn) { + case SA_DEVFN_CPU_PCIE1_0: + return CPU_CPIE_VW_IDX_BASE; + case SA_DEVFN_CPU_PCIE6_0: + return CPU_CPIE_VW_IDX_BASE + 3; + case SA_DEVFN_CPU_PCIE6_2: + return CPU_CPIE_VW_IDX_BASE + 2; + default: + return -1; + } +} |