diff options
| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-06-14 22:20:28 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-24 20:33:48 +0200 |
| commit | 3dbea29ee65c99ae09690765f20869b46464e66a (patch) | |
| tree | f7eb3a63d668fc68e99d503162d81c3cbc99069e | |
| parent | 33fd66b46309b140ed9b228083a55a394117afea (diff) | |
soc/intel/apollolake: Implement global reset handling
Global reset enable bit is not cleared on reset. Therefore, clear
the bit early. Lock down 0xcf9 so that payload/OS can't issue
global reset.
BUG=chrome-os-partner:54149
BRANCH=none
TEST=none
Change-Id: I3ddf6dd82429b725c818bcd96e163d2ca0acd308
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15199
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
| -rw-r--r-- | src/soc/intel/apollolake/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 6 |
3 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index d67a6bd833..7326f1448f 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -15,6 +15,7 @@ bootblock-y += car.c bootblock-y += gpio.c bootblock-y += lpc_lib.c bootblock-y += mmap_boot.c +bootblock-y += pmutil.c bootblock-y += spi.c bootblock-y += tsc_freq.c bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 84130756ed..8c1ff919d1 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -25,6 +25,7 @@ #include <soc/mmap_boot.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> +#include <soc/pm.h> #include <soc/uart.h> #include <spi-generic.h> #include <timestamp.h> @@ -153,6 +154,9 @@ void bootblock_soc_early_init(void) { enable_pmcbar(); + /* Clear global reset promotion bit */ + global_reset_enable(0); + /* Prepare UART for serial console. */ if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) soc_console_uart_init(); diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index dd4a0a56e8..ddb1374ddf 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -32,6 +32,7 @@ #include <soc/nvs.h> #include <soc/pci_devs.h> #include <spi-generic.h> +#include <soc/pm.h> #include "chip.h" @@ -93,6 +94,11 @@ static void soc_final(void *data) { if (vbt) rdev_munmap(&vbt_rdev, vbt); + + /* Disable global reset, just in case */ + global_reset_enable(0); + /* Make sure payload/OS can't trigger global reset */ + global_reset_lock(); } void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) |