diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2017-11-10 13:16:23 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-10 22:01:22 +0000 |
| commit | 36dbf1d74a8797b49984c98df748c1d526831e53 (patch) | |
| tree | c4e703ac7464061721a87de6786107bd4f1d8096 | |
| parent | bf131b26165125d452b694ef83926c2c32bf99d0 (diff) | |
soc/amd/stoneyridge: Add UMA settings to devicetree
Add three settings for the UMA configuration to correspond with
definitions in AGESA.h.
* UMA off, Auto, or size specified
* Size (if specified above)
* Legacy vs. non-legacy (if Auto)
BUG=b:64927639
Change-Id: I38b6603f365fdc1f1f615794365476f749e58be7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/soc/amd/stoneyridge/chip.h | 16 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/romstage.c | 23 |
2 files changed, 39 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 4623800848..f50851b44b 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -16,7 +16,9 @@ #ifndef __STONEYRIDGE_CHIP_H__ #define __STONEYRIDGE_CHIP_H__ +#include <stddef.h> #include <stdint.h> +#include <commonlib/helpers.h> #define MAX_NODES 1 #define MAX_DRAM_CH 1 @@ -28,6 +30,20 @@ struct soc_amd_stoneyridge_config { DRAM_CONTENTS_KEEP, DRAM_CONTENTS_CLEAR } dram_clear_on_reset; + + enum { + /* Do not enable UMA in the system. */ + UMAMODE_NONE, + /* Enable UMA with a specific size. */ + UMAMODE_SPECIFIED_SIZE, + /* Let AGESA determine the proper size. Non-legacy requires + * the resolution to be specified PLATFORM_CONFIGURATION */ + UMAMODE_AUTO_LEGACY, + UMAMODE_AUTO_NON_LEGACY, + } uma_mode; + + /* Used if UMAMODE_SPECIFIED_SIZE is set. */ + size_t uma_size; }; typedef struct soc_amd_stoneyridge_config config_t; diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 9b22761f9e..06000ffd92 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -119,9 +119,32 @@ void SetMemParams(AMD_POST_PARAMS *PostParams) if (!dev || !dev->chip_info) { printk(BIOS_ERR, "ERROR: Could not find SoC devicetree config\n"); + /* In case of a BIOS error, only attempt to set UMA. */ + PostParams->MemConfig.UmaMode = IS_ENABLED(CONFIG_GFXUMA) ? + UMA_AUTO : UMA_NONE; return; } cfg = dev->chip_info; + PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset; + + switch (cfg->uma_mode) { + case UMAMODE_NONE: + PostParams->MemConfig.UmaMode = UMA_NONE; + break; + case UMAMODE_SPECIFIED_SIZE: + PostParams->MemConfig.UmaMode = UMA_SPECIFIED; + /* 64 KiB blocks. */ + PostParams->MemConfig.UmaSize = cfg->uma_size / (64 * KiB); + break; + case UMAMODE_AUTO_LEGACY: + PostParams->MemConfig.UmaMode = UMA_AUTO; + PostParams->MemConfig.UmaVersion = UMA_LEGACY; + break; + case UMAMODE_AUTO_NON_LEGACY: + PostParams->MemConfig.UmaMode = UMA_AUTO; + PostParams->MemConfig.UmaVersion = UMA_NON_LEGACY; + break; + } } |