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| author | Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> | 2021-09-22 20:50:33 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-23 14:38:51 +0000 |
| commit | 3673a1654663dfa5dfa255e95c90d59f60095f2d (patch) | |
| tree | 3f35120f34367e86fd5f4bad23943ec2c8a93d35 | |
| parent | b0d87f753c9c517ba906115362d32aa4422fd188 (diff) | |
mb/google/brya/variants/gimble: Update audio setting
Add vmon-slot-no,imon-slot-no and dsm_param_file_name in overridetree.cb
BUG=b:197701952
TEST=build and check SSDT
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie646360c4ebbf25762b374c5bc3ef2017989fb2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57832
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/gimble/overridetree.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index c2949c4877..792195291d 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -124,6 +124,9 @@ chip soc/intel/alderlake register "name" = ""MXW0"" register "r0_calib_key" = ""dsm_calib_r0_0"" register "temperature_calib_key" = ""dsm_calib_temp_0"" + register "dsm_param_file_name" = ""dsm_param"" + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" device i2c 0x38 on end end @@ -133,6 +136,9 @@ chip soc/intel/alderlake register "name" = ""MXW1"" register "r0_calib_key" = ""dsm_calib_r0_1"" register "temperature_calib_key" = ""dsm_calib_temp_1"" + register "dsm_param_file_name" = ""dsm_param"" + register "vmon_slot_no" = "1" + register "imon_slot_no" = "0" device i2c 0x3c on end end |