diff options
author | Felix Held <felix-coreboot@felixheld.de> | 2021-03-25 01:20:41 +0100 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2021-03-29 19:07:48 +0000 |
commit | 27b295b98b65e05635ee5a40967adb0f9ca79afa (patch) | |
tree | f58f81148a507288b56c2a366f18753d58dbc0fc | |
parent | 2c62df229f49b7dde6a9ad5d963153582efb6822 (diff) |
soc/amd: add DISABLE_KEYBOARD_RESET_PIN option
The KBRST_L pin will cause a reset when driven or pulled low even when
the GPIO mux is set to GPIO and not native function. So when you want to
use that pin as general purpose output the keyboard reset input
functionality needs to be disabled by selecting this option in the
board's Kconfig file to avoid causing a reset by writing a 0 to the
output level bit when it's configured as an output.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: I517ad551db9321f26afdba15d97ddb61be1f7d51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r-- | src/soc/amd/cezanne/Kconfig | 8 | ||||
-rw-r--r-- | src/soc/amd/cezanne/early_fch.c | 4 | ||||
-rw-r--r-- | src/soc/amd/picasso/Kconfig | 8 | ||||
-rw-r--r-- | src/soc/amd/picasso/early_fch.c | 4 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/Kconfig | 8 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 4 |
6 files changed, 36 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 9a108c95fb..3d672d8de7 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -204,6 +204,14 @@ config DISABLE_SPI_FLASH_ROM_SHARING removes arbitration with board and assumes the chipset controls the SPI flash bus entirely. +config DISABLE_KEYBOARD_RESET_PIN + bool + help + Instruct the SoC to not use the state of GPIO_129 as keyboard reset + signal. When this pin is used as GPIO and the keyboard reset + functionality isn't disabled, configuring it as an output and driving + it as 0 will cause a reset. + menu "PSP Configuration Options" config AMD_FWM_POSITION_INDEX diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 4e7d84d389..0c72863ba3 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -52,6 +52,10 @@ void fch_pre_init(void) if (CONFIG(AMD_SOC_CONSOLE_UART)) set_uart_config(CONFIG_UART_FOR_CONSOLE); + + /* disable the keyboard reset function before mainboard GPIO setup */ + if (CONFIG(DISABLE_KEYBOARD_RESET_PIN)) + fch_disable_kb_rst(); } /* After console init */ diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 1fca390fea..b6ab78494a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -320,6 +320,14 @@ config DISABLE_SPI_FLASH_ROM_SHARING removes arbitration with board and assumes the chipset controls the SPI flash bus entirely. +config DISABLE_KEYBOARD_RESET_PIN + bool + help + Instruct the SoC to not use the state of GPIO_129 as keyboard reset + signal. When this pin is used as GPIO and the keyboard reset + functionality isn't disabled, configuring it as an output and driving + it as 0 will cause a reset. + config MAINBOARD_POWER_RESTORE def_bool n help diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index 1aff83b5c8..63e192fa7f 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -62,6 +62,10 @@ void fch_pre_init(void) if (CONFIG(AMD_SOC_CONSOLE_UART)) set_uart_config(CONFIG_UART_FOR_CONSOLE); + + /* disable the keyboard reset function before mainboard GPIO setup */ + if (CONFIG(DISABLE_KEYBOARD_RESET_PIN)) + fch_disable_kb_rst(); } /* After console init */ diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 5f1b65a476..adce99cfae 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -371,6 +371,14 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 +config DISABLE_KEYBOARD_RESET_PIN + bool + help + Instruct the SoC to not use the state of GPIO_129 as keyboard reset + signal. When this pin is used as GPIO and the keyboard reset + functionality isn't disabled, configuring it as an output and driving + it as 0 will cause a reset. + config MAINBOARD_POWER_RESTORE def_bool n help diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 161e3e8897..28310ce709 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -344,6 +344,10 @@ void bootblock_fch_early_init(void) fch_enable_legacy_io(); enable_aoac_devices(); + + /* disable the keyboard reset function before mainboard GPIO setup */ + if (CONFIG(DISABLE_KEYBOARD_RESET_PIN)) + fch_disable_kb_rst(); } /* After console init */ |