diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-05-07 14:29:13 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-05-14 15:08:11 +0000 |
| commit | 2412924bc7646fc22b2cb1b9108413fa3e849082 (patch) | |
| tree | 0ce0b509a1470ace469133bdb061e27857709f7e | |
| parent | cc35f723fdcc6999ace18eae18467b900a12c07f (diff) | |
mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports
This change enables PCIEXP_HOTPLUG to support resource allocation for
TCSS TBT/USB4 ports.
BUG=b:149186922
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4cb820e83da40434b00198b934453805e35ef1ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/mainboard/google/volteer/Kconfig | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index de77633153..68759636a0 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 + select PCIEXP_HOTPLUG select SOC_INTEL_TIGERLAKE if BOARD_GOOGLE_BASEBOARD_VOLTEER @@ -66,6 +67,20 @@ config MAX_CPUS int default 8 +# Reserving resources for PCIe Hotplug as per TGL BIOS Spec (doc #611569) +# Revision 0.7.6 Section 7.2.5.1.5 +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c000000 # 448 MiB + config TPM_TIS_ACPI_INTERRUPT int default 21 # GPE0_DW0_21 (GPP_C21) |